Fast and accurate hybrid power estimation methodology for embedded systems

Rethinagiri, Santhosh Kumar; Atitallah, Rabıe Ben; Niar, Smaïl; Senn, Eric; Dekeyser, Jean-Luc

doi:10.1109/dasip.2011.6136852

Cited by 7 publications

(4 citation statements)

References 10 publications

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“…In this work, we propose to couple the OVPSim simulator with the functional level power models which offers reasonable trade-off between estimation speed and accuracy. In our previous work [15] [17], we introduced this methodology for power estimation of mono-processor based platforms and proved to be accurate and faster than the state-of-the-art tools ant this methodology was extended to accOlmnodate DSP processor based platforms [16]. In this paper, we propose power/energy estimation for complex multi core/processor based heterogeneous platforms at system-level and also propose a reliable design space exploration based on energy for the applications involving heterogeneous architec tures.…”

Section: S �mentioning

confidence: 99%

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri

Palomar

Moreno

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

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Using low-power symmetric multi-cores on FPGAs are becoming ubiquitous in embedded computing. This is due to the emergence of power and energy as key design metrics, as important as performance. This leads to the requirement of powerful and reliable tools, which will be used for the Design Space Exploration (DSE) based on power and energy at an early stage of the design flow. In this paper, we propose a simulation based virtual platform power and energy estimation tool for heterogeneous Multiprocessor System-on-Chip (MPSoC) based platforms. There are two steps involved in this tool development.The first step is power model generation. For the power model development, we used functional parameters to set up generic power models for different parts of the system. This is a one-time activity. In the second step, a simulation based virtual platform framework is developed to accurately grab the activities used in the related power models generated in the first step. The combination of the two steps leads to a hybrid power estimation, which gives a better trade-off between accuracy and speed.The proposed tool is automated and also scalable for exploring complex embedded multi-core architectures. The efficiency of the proposed tool is validated through multi-cores/processors designed around the FPGAs and extended to accommodate futuristic multi-processors/cores for a reliable energy based DSE.The obtained power/energy estimation results provide less than 4% of error for single core processor, 8% for dual-core processor and 9% for heterogeneous MPSoC based systems when compared to real board measurements.

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Section: S �mentioning

confidence: 99%

VPPET: Virtual platform power and energy estimation tool for heterogeneous MPSoC based FPGA platforms

Rethinagiri

Palomar

Moreno

et al. 2014

2014 24th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)

Self Cite

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“…This tool simplifies application porting as well as enables the user to choose the processor architecture upon which to perform hardware/software co-simulation. PETS was initially developed for the evaluation of MPSoC systems [10], [9], [11]. In ParaDIME, we have extended it to model a variety of other systems, including DSPs, FPGAs and multi-core (dual-and quad-core) ARM processors [13], [12], [15].…”

Section: ) Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy

Rethinagiri

Palomar

Sobe

et al. 2014

2014 17th Euromicro Conference on Digital System Design

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“…This, in turn, leads to the need for new and simpler simulation frameworks for fast, accurate, and hassle-free energy estimation at higher abstraction levels. Indeed, several embedded energy/power estimation methods have been developed over last decade that employ various techniques, such as instruction-set-level energy/power estimation, 4 run-time performance counter-based energy/power estimation, 5 high-level energy macro-modeling, 6 functional-level energy/power analysis, 7 etc. All of these frameworks have been motivated by the importance of reducing energy consumption in embedded systems.…”

Section: Introductionmentioning

confidence: 99%