Fan-Out Chip on Substrate Device Interconnection Reliability Analysis

Lee, Ying-Chih; Lai, Wei‐Hong; Hu, Ian; Shih, Meng-Kai; Kao, C. R.; Tarng, David; Hung, Chih-Pin

doi:10.1109/ectc.2017.104

Cited by 30 publications

(2 citation statements)

References 7 publications

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“…As a result, local deformation of the silicon chip is caused by the mismatch between different thermal expansion coefficients of the silicon chip and copper pillar. The structural signature of flip-chip packages could generate high localized stress and might cause not only deterioration of bonding reliability, such as delamination or cracking [2]- [8], but also circuit performance fluctuation due to the piezoelectric effect of active circuits [9]- [15]. In response to those concerns, we have designed a new test vehicle to evaluate local stress distribution in a flip-chip package.…”

Section: Introductionmentioning

confidence: 99%

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

Ueda

Watanabe

2019

IEEE Trans. Compon., Packag. Manufact. Technol.

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The local stress distribution in a silicon chip encapsulated in an area-arrayed copper pillar-type flip-chip package was evaluated using specially designed test chips. Stress is sensed using piezoelectric resistors, which are p-type and n-type diffusion resistors embedded in a silicon chip measuring 7.8 mm × 7.8 mm. Each piezoelectric resistor measures approximately 0.03 mm in length and 0.002 mm in width, which is sufficiently small to measure the local stress distribution near each copper pillar. As a result of this study, it is revealed that the copper pillars have an impact on the local stress distribution in silicon chips, in particular producing a large stress gradient near the copper pillar edge, compared to the conventional wire-bonded packages. Since large stress gradients disturb pair characteristics of analog circuits, in order to design a high-precision integrated circuit employing a copper pillar-type flip-chip package, a specific regulation method to avoid overlap with the copper pillars is needed to maintain the accuracy of the analog circuits.

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Section: Introductionmentioning

confidence: 99%

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

Ueda

Watanabe

2019

IEEE Trans. Compon., Packag. Manufact. Technol.

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“…

analyzing and understanding the internal physical and chemical properties of device and their failure mechanisms during application, improvements in device design, manufacturing, application, and material technology could be realized. [7][8][9][10][11][12] However, the miniaturization and multi disciplinary crosscutting of electronic products bring more complex microstruc tures, and the analysis becomes more challenging. [13] To solve this problem, it is important to adopt advanced failure analysis technology with high spatial reso lution and develop corresponding sample preparation methods to precisely locate the failure spot.Transmission electron microscopy (TEM) technology is a powerful tool for device analysis with atomic resolu tion.

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mentioning

confidence: 99%

The Trends of In Situ Focused Ion Beam Technology: Toward Preparing Transmission Electron Microscopy Lamella and Devices at the Atomic Scale

Zhang

Wang

Dong

et al. 2022

Adv Elect Materials

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The increased complexity and scaling down of electronic devices lead to great challenges in extracting an interesting nanoscale area of the device for transmission electron microscopy (TEM) characterization. The traditional TEM sample preparation methods, such as electrolytic polishing, can not precisely process a specific area of the device. Focused ion beam (FIB) technology is an advanced in situ specimen preparation method for TEM. FIB can not only locate specific position and mill a TEM sample with the nanoscale resolution, but also manipulate the sample in a controlled manner in real time. With the development of electronic devices, variations, and optimizations of the FIB method for advanced devices with new structures have been reported. In this review, the TEM sample preparation methods for fin field‐effect transistor, high electron mobility transistor, enhanced dynamic random‐access memory, and 2D material‐based devices are discussed. Their advantages, disadvantages, and an overview of the applications are summarized. Based on current research, future research directions for enhancing the quality of TEM samples are suggested.

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Heterogeneous Integrations on Fan-Out RDL Substrates

Lau

2019

Heterogeneous Integrations

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Fan-Out Chip on Substrate Device Interconnection Reliability Analysis

Cited by 30 publications

References 7 publications

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

Impact of Local Stress Distribution in a Silicon Chip Mounted by Area-Arrayed Copper Pillar Wafer-Level Packaging Technology on Analog-Circuit Performance

The Trends of In Situ Focused Ion Beam Technology: Toward Preparing Transmission Electron Microscopy Lamella and Devices at the Atomic Scale

Heterogeneous Integrations on Fan-Out RDL Substrates

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