Families of FPGA-based algorithms for approximate string matching

Court, T. Van; Herbordt, Martin C.

doi:10.1109/asap.2004.1342484

Cited by 29 publications

(35 citation statements)

References 16 publications

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“…One example of an application family addresses approximate string matching [15]. In that case study, the character strings may be DNA with a four-letter (two bit) alphabet, protein sequences composed of 20-letters (five bits each), IUPAC wildcards (four bits), codons (six bits), or any other type the user chooses.…”

Section: Application Familiesmentioning

confidence: 99%

“…[6] Much of this difficulty comes from the need to manage an FPGA's biggest advantage, its inherently massive, fine grained parallelism. In many applications, however, well understood repetitive structures such as systolic arrays can be used to manage the parallelism [15] [16]. These offer the possibility of effectively unbounded growth of computation arrays as FPGA sizes increase, with the promise of increased application throughput or of increased problem sizes.…”

Section: Introductionmentioning

confidence: 99%

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Sizing of Processing Arrays for FPGA-Based Computation

VanCourt

Herbordt

2006

2006 International Conference on Field Programmable Logic and Applications

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Computing applications in FPGAs are commonly built from repetitive structures of computing and/or memory elements. In many cases, application performance depends on the degree of parallelism -ideally, the most that will fit into the fabric of the FPGA being used. Several factors complicate determination of the largest structure that will fit the FPGA: arrays that grow polynomially and trees that grow exponentially, coupled structures that grow in different polynomial order, multiple design parameters controlling different aspects of the computing structure, and interlocked usage of different hardware resources. Combined with resource usage that depends on application-specific data elements and arithmetic details, these factors defeat any simple approach for scaling the computing structures up to the FPGA's capacity. We present an analytic framework for maximizing FPGA utilization, including features for efficient exploration of array size alternatives. We also report on design tools containing extensions that support automated sizing of FPGA-based computation arrays.

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Section: Application Familiesmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Sizing of Processing Arrays for FPGA-Based Computation

VanCourt

Herbordt

2006

2006 International Conference on Field Programmable Logic and Applications

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“…In [18] and [19], the authors propose the first FPGA-based accelerator that supports affine gap penalty. Systolic matching cells are implemented to support different cost functions and alignment algorithms such as the Needleman-Wunsch or Smith-Waterman.…”

Section: A Pairwise Sequence Alignmentmentioning

confidence: 99%

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Liu

Luk

2017

2017 27th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Genetic sequence alignment has always been a computational challenge in bioinformatics. Depending on the problem size, software-based aligners can take multiple CPUdays to process the sequence data, creating a bottleneck point in bioinformatic analysis flow. Reconfigurable accelerator can achieve high performance for such computation by providing massive parallelism, but at the expense of programming flexibility and thus has not been commensurately used by practitioners. Therefore, this paper aims to provide a thorough survey of the proposed accelerators by giving a qualitative categorization based on their algorithms and speedup. A comprehensive comparison between work is also presented so as to guide selection for biologist, and to provide insight on future research direction for FPGA scientists.

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“…In terms of the AM matrix, this means that the anti-diagonal values can be calculated concurrently, see Figure 2c. This property is effectively used for algorithm acceleration using dedicated hardware (Hoang and Lopresti, 1992) (Lavenier, 1998) (Yu et al, 2003) (Court and Herbordt, 2004). Typical hardware architecture is based on a systolic array of Processing Elements (PE) (see Figure 2c).…”

Section: Needleman-wunsch Hardware Accel-erationmentioning

confidence: 99%

Genomic PCR Simulation With Hardware-Accelerated Approximate Sequence Matching

Lexa¹,

Martínek²,

Beck³

et al. 2007

ECMS 2007 Proceedings Edited By: I. Zelinka, Z. Oplatkova, A. Orsoni

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We report the latest details on improvements made or planned for the VPCR simulation software currently accessible on the Internet (installed on servers in Padova and Brno). We describe the inner workings of the dynamic amplification simulation model, concentrating mostly on the time-and sensitivity-critical step of sequence matching. Replacement of BLAST by the more sensitive and faster PRIMEX similarity search program resulted in a marked improvement of PCR product predictions. Further speed improvements were acheived using hardware acceleration of approximate sequence matching. We report our theorethical computation time estimates and results of the first tests using the Arabidopis and human genome sequences as PCR templates.

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Families of FPGA-based algorithms for approximate string matching

Cited by 29 publications

References 16 publications

Sizing of Processing Arrays for FPGA-Based Computation

Sizing of Processing Arrays for FPGA-Based Computation

Reconfigurable acceleration of genetic sequence alignment: A survey of two decades of efforts

Genomic PCR Simulation With Hardware-Accelerated Approximate Sequence Matching

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