Fair comparison of hardware and software LDPC decoder implementations for SDR space links

Pignoly, Vincent; Gal, Bertrand Le; Jégo, Christophe; Gadat, Benjamin; Barthe, Lyonel

doi:10.1109/icecs49266.2020.9294906

Cited by 3 publications

(3 citation statements)

References 12 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Since the emulation of FF operations requires a large number of instructions 21 (thus slowing down the performance of the processor), some researchers decided to use extremely powerful GPPs and/or graphical processing units (GPUs). However, even this very expensive approach has not proven to be applicable [22][23][24][25] in future communication networks (Table 3). Unlike FF-based codes, IECCs are perfectly suited for implementation on 64-bit processors.…”

Section: Discussionmentioning

confidence: 99%

Logarithmic time encoding and decoding of integer error control codes

Radonjić

Vujičić

2023

Engineering Reports

View full text Add to dashboard Cite

One of the most important characteristics of all error control codes (ECCs) is the complexity of the encoding/decoding algorithms. Today, there are many ECCs that can correct multiple bit errors, but at the price of high encoding/decoding complexity. Among the rare exceptions are integer ECCs (IECCs), whose serial encoding/decoding algorithms run in O(n) time, where n is the codeword length. In this article, we show that IECCs can be encoded/decoded even faster, that is, that their parallel encoding/decoding algorithms have O(log2n) time complexity.

show abstract

Section: Discussionmentioning

confidence: 99%

Logarithmic time encoding and decoding of integer error control codes

Radonjić

Vujičić

2023

Engineering Reports

View full text Add to dashboard Cite

show abstract

“…Although more flexible and scalable than application-specific integrated circuit (ASIC)-based designs, industrial systems have limitations. Energy consumption and thermal dissipation [19] of these architectures strongly exceed embedded IoT typical constraints. A number of academic [20]- [22] and industrial proposals [22] exist that make the design of optimized hardware architectures possible.…”

Section: Related Workmentioning

confidence: 99%

Extended RISC-V hardware architecture for future digital communication systems

Tourres

Gal

Crenne

et al. 2021

2021 IEEE 4th 5G World Forum (5GWF)

View full text Add to dashboard Cite

HAL is a multi-disciplinary open access archive for the deposit and dissemination of scientific research documents, whether they are published or not. The documents may come from teaching and research institutions in France or abroad, or from public or private research centers. L'archive ouverte pluridisciplinaire HAL, est destinée au dépôt et à la diffusion de documents scientifiques de niveau recherche, publiés ou non, émanant des établissements d'enseignement et de recherche français ou étrangers, des laboratoires publics ou privés.

show abstract

“…For the implementation of ECC, a digital signal processor (DSP) or field programmable gate array (FPGA) is known to be more faster and energy-efficient than software-based implementation [10]. For the low-latency applications, the BECC is often implemented as a DSP or logic modules in the transceiver for the physical layer.…”

Section: Introductionmentioning

confidence: 99%

New Design of Error Control Codes Resilient to Single Burst Error or Two Random Bit Errors Using Constacyclic Codes

Kim

2022

IEEE Access

View full text Add to dashboard Cite

In this paper, we introduce a new design method of burst error control codes (BECCs), which can correct single burst error or two random bit errors by using the maximum likelihood syndrome decoder (MLSD), where the proposed BECCs are designed by a modification of the well-known Fire codes using constacyclic codes. Also, for the existing low-latency burst error-correcting decoder, it is shown that the proposed BECCs have the single burst error correction capability together with two random bit error detection capability with no additional parity bits and comparable complexity with the existing BECCs. For this, the complexity and latency is numerically analyzed by register-transfer level (RTL) synthesis.INDEX TERMS Burst error control codes (BECCs), burst errors, error control codes, Fire codes, lowlatency decoder

show abstract

Fair comparison of hardware and software LDPC decoder implementations for SDR space links

Cited by 3 publications

References 12 publications

Logarithmic time encoding and decoding of integer error control codes

Logarithmic time encoding and decoding of integer error control codes

Extended RISC-V hardware architecture for future digital communication systems

New Design of Error Control Codes Resilient to Single Burst Error or Two Random Bit Errors Using Constacyclic Codes

Contact Info

Product

Resources

About