Failure Analysis of Oxide Defects

Techniques for measuring the integrity of passivation overcoats on integrated circuits

“…Pinholes in the glass overcoat may also be caused by aluminum grain growth during CVD [8,9] or by impact during chip handling [1,9,10]. Cracks in the CVD oxide or glass passivation over aluminum in linear bipolar ICs seem to be the cause of increased susceptibility of metal corrosion during device operation, which led to serious field failure [11,12],…”

“…Examples of decoration methods are: electrophoretic particle transport techniques [1] and electrolytic decoration with copper oxysalts [14,15]. Methods based on reaction at the defect sites are nematic liquid-crystal light-scattering in an electric field to produce readily visible vortices above the defects [8,16]; formation of trains of hydrogen gas bubbles rising from the defect sites [14] ; electroautographic techniques [14]; and self-limiting dielectric breakdown [17] where a deposited thin-metal film electrode disrupts, indicating the location of a defect.…”

Passivation Coatings on Silicon Devices

“…Our experimental studies (156) have shown that in a substantial portion of the integrated circuits manufactured in the last several years, the passivation layer contains pinholes, cracks, or a combination of these. A number of publications also confirm this finding (157,278,140,144,210,89,153,338,21).…”

“…Pinholes in the dielectric over alloyed metal are generally very difficult to see by optical microscopy because of the rough topography of the recrystallized aluminum. Both cracks and pinholes can be revealed by scanning electron microscopy (SEM), or by subjecting the chip to immersion in an etchant which does not dissolve the dielectric but is calcable of dissolving the underlying material (85,254,144,89,153). After chemical etching to undercut the A1, the actual pinhole in the dielectric is generally visible, by optical microscopy, in the center of the undercut area (153).…”

An Improved Approach to Locating Pinhole Defects in MOS and Bipolar Integrated Circuits Using Liquid Crystals

“…This step limits the area which must be examined in detail in subsequent steps. 4. Exposure of the Suspect Oxide -Enabling the failure analyst to thoroughly study the suspect oxide under the optical microscope, to attempt precise location and verification of the oxide defect and perhaps establish the defect mechanism.…”