Failure analysis of 6t sram on low-voltage and high-frequency operation

Ikeda, Shuji; Yoshida, Yoshinori; Ishibashi, Koji; Mitsui, Yasuhiro

doi:10.1109/ted.2003.813474

Cited by 28 publications

(10 citation statements)

References 10 publications

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“…The detailed device fabrication process is described elsewhere. 15 Bitmaps of failure memories were acquired at wafer level test for 1.2 V and at reduced voltages using a Teradyne J750 device tester. Failure signatures were inspected with a BVIEWNG bitmap viewing software.…”

Section: Experimental Methodsmentioning

confidence: 99%

Advance static random access memory soft fail analysis using nanoprobing and junction delineation transmission electron microscopy

Chang

Hsieh

Zimmermann³

et al. 2007

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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Nanoprobing was used to analyze the soft cell failure of submicron static random access memory (SRAM) at cell level by means of a Zyvex S100 nanomanipulator system inside a scanning electron microscopy and a multiprobe atomic force probe system, respectively. For the 256Kbyte dual-port SRAM block, the failure areas exhibit very weak positive-channel field effect transistor drain currents of several magnitudes below the target values, while the drain currents of negative-channel field effect transistor cell transistors are in the expected range. A junction delineation or junction stain was applied to transmission electron microscopy samples to delineate areas with different doping levels so as to make the fail sites visible. Due to the difference in etching behavior of the fail and a reference area, missing lightly doped drain extensions and a partially blocked source/drain implantation were identified as the failure mechanisms.

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Section: Experimental Methodsmentioning

confidence: 99%

Advance static random access memory soft fail analysis using nanoprobing and junction delineation transmission electron microscopy

Chang

Hsieh

Zimmermann³

et al. 2007

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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“…Among the reliability concerns, pMOS V th variations become more and more difficult to control in small devices which brings about decreased V min margin. Although nanoprober technique has been utilized for measuring local failure bits [1], further understanding of failure mechanism requires direct visualization of carrier distribution within the poly-Si gate. Scanning spreading resistance microscopy (SSRM) has been reported 1-nm-spatial resolution recently [2,3], and the newly developed sampling-making method by FIB pick up (PU) enables analysis of site-specific characterization [4].…”

Section: Introductionmentioning

confidence: 99%

Direct visualization of anomalous-phosphorus diffusion in failure-bit gates of SRAM-load pMOSFETs with high-resolution scanning spreading resistance microscopy

Zhang

Hara

Kinoshita

et al. 2010

2010 International Electron Devices Meeting

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In this study, we directly observed fail bits of pMOS with V th variations in SRAM by both SSRM and a nanoprober, clarified that the failure is originated from the phosphorus anomalous diffusion into the pMOS gate bottom. We succeeded in observing the pn-junction boundary within a thin SRAM poly-Si gate with the size of less than 60 nm. The gate-phosphorus doping and STI geometry influence on pn boundary is investigated systematically. A significant improvement in process margin is achieved with controlling of the phosphorous-anomalous diffusion.

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“…Snyder et al 6 analyzed reasons for failure of chips working at very high frequency. Ikeda et al 7 and Yoshida et al 8 used techniques such as nanoprobes, selective etching and TEM observations to analyze bit failures at low voltage and high operating speed.…”

Section: Introductionmentioning

confidence: 99%

On-board SRAM signal density stress prediction

Hsieh

Sharma

2006

SPIE Proceedings

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Static Random Access Memory (SRAM) chips undergo several types of stress in the field. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on signal density stress prediction. Objectives of this study were to (1) explore the impact of signal density stress on SRAM functionality, (2) observe thermal profile differences under signal density stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for signal density stress prediction. An 8051 programming board containing an SRAM chip was used. Two kinds of signal density stress were investigated-varying the content written to memory, and varying signal frequency in accessing SRAM through flash memory. Preliminary experiments suggest that both types of stress impact the SRAM thermal profile. Thermal profile data were used to build back propagation neural network models; 70% of the data was used to build the models and 30% was used for testing. Various neural network training functions and topologies were used to predict chip stress level given thermal profile data. Data from both the die area and the entire chip were used. For both types of stress, using data from the die area in a network with a 3-3-1 topology yielded the lowest average error rate-1.3% for data content stress level prediction and 7.6 % for signal frequency stress level prediction. The trainRP function resulted in a lower error rate than other training functions that were evaluated.

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Failure analysis of 6t sram on low-voltage and high-frequency operation

Cited by 28 publications

References 10 publications

Advance static random access memory soft fail analysis using nanoprobing and junction delineation transmission electron microscopy

Advance static random access memory soft fail analysis using nanoprobing and junction delineation transmission electron microscopy

Direct visualization of anomalous-phosphorus diffusion in failure-bit gates of SRAM-load pMOSFETs with high-resolution scanning spreading resistance microscopy

On-board SRAM signal density stress prediction

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