Failure analysis methodology for the localization of thin and ultra-thin metal barrier residue

This paper describes the observation of photoemissions from saturated transistors along a connecting path with open defect in the logic array. By exploiting this characteristic phenomenon to distinguish open related issues, we described with 2 case studies using Photon Emission Microscopy, CAD navigation and layout tracing to identify the ‘open’ failure path. Further layout and EBAC analysis are then employed to effectively localize the failure site.

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Failure analysis methodology for the localization of thin and ultra-thin metal barrier residue

Cited by 2 publications

References 4 publications

Defect Prediction Approach to enhance Static Fault Localization of Functional Logic Failure Defects using NIR Photon Emission Microscopy

Defect Prediction Approach to enhance Static Fault Localization of Functional Logic Failure Defects using NIR Photon Emission Microscopy

Failure Analysis Methodology on Resistive Open Defects

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