Fail Memory Configuration Set for RA Estimation

Lee, Hayoung; Cho, Keewon; Kang, Sungho; Kang, Wooheon; Lee, Seungtaek; Jeong, Wooyoung

doi:10.1109/itc44778.2020.9325273

Cited by 11 publications

(3 citation statements)

References 37 publications

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“…In the memory used in the experiments, an address is allocated to a byte of memory cells. For simulation, the ITC 2020 benchmark RA models [42], which are authorized fail memory configuration sets for objective RA performance estimations, are considered as a reference. In the simulation, the number of faults distributed in the entire stacked memory is varied, and the number of faults assigned to each layer is random.…”

Section: Resultsmentioning

confidence: 99%

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

2021

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The memory cell density and memory capacity have been increased for obtaining larger and faster memory. However, this threatens the memory reliability by increasing the probability of faulty cell generation. In this paper, a fast and small-area built-in redundancy analysis (RA) for the post-bond repair process in 3D memory is proposed. Spare line allocation is the structure for memory repair which the most widely used. However, the spare line structure that replaces the entire line which contains faults in each memory layer occurs inefficiency in repairing a small number of faults, including single faults, and it is difficult to share spares between layers. The proposed idea is to use spare line to repair line faults according to the characteristics of it, and to complement the structural limitations by proposing a new redundant spare. This is base common spare located on the base die, and it can be shared across all layers. The proposed BIRA improves the efficiency of spare lines with two complementary spare resource structures, achieving a short repair time and high repair rate. The proposed BIRA achieves 100% repair rate when there are at least 2 times more faults than the previous works with the same hardware overhead. In addition, it takes only at most 80% of the analysis time compared to the previous works, and as the number of faults increases, the analysis time reduction becomes greater compared to the previous works.INDEX TERMS built-in redundancy analysis (BIRA), built-in self-repair (BISR), built-in self-test (BIST), memory repair, repair rate, yield improvement

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Section: Resultsmentioning

confidence: 99%

Effective Spare Line Allocation Built-in Redundancy Analysis With Base Common Spare for Yield Improvement of 3D Memory

2021

Self Cite

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“…Lee et al [55] presented a methodology to generate a set of memory configurations that can be used to compare the efficiency of various redundancy analysis algorithms. It considers memory models with various redundancy structures.…”

Section: Simulators For Measuring Reliability and Repair Efficiencymentioning

confidence: 99%

“…Atishay et al [57] presented a statistical error and redundancy analysis simulator which generates faults similar to the manufacturing environment for DRAM. Most other fault simulators, including [55], generate defects randomly or use Binomal or Polya-Eggenberger distribution model, which does not represent defects on wafers. These simulators also lack in considering defects from evolving DRAM technologies.…”

Section: Simulators For Measuring Reliability and Repair Efficiencymentioning

confidence: 99%

Memory built-in self-repair and correction for improving yield: a review

Sontakke,

Atchina

2024

IJECE

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Nanometer memories are highly prone to defects due to dense structure, necessitating memory built-in self-repair as a must-have feature to improve yield. Today’s system-on-chips contain memories occupying an area as high as 90% of the chip area. Shrinking technology uses stricter design rules for memories, making them more prone to manufacturing defects. Further, using 3D-stacked memories makes the system vulnerable to newer defects such as those coming from through-silicon-vias (TSV) and micro bumps. The increased memory size is also resulting in an increase in soft errors during system operation. Multiple memory repair techniques based on redundancy and correction codes have been presented to recover from such defects and prevent system failures. This paper reviews recently published memory repair methodologies, including various built-in self-repair (BISR) architectures, repair analysis algorithms, in-system repair, and soft repair handling using error correcting codes (ECC). It provides a classification of these techniques based on method and usage. Finally, it reviews evaluation methods used to determine the effectiveness of the repair algorithms. The paper aims to present a survey of these methodologies and prepare a platform for developing repair methods for upcoming-generation memories.

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