“…5(a), was fabricated on a SOI wafer (top silicon layer: 250 nm, buried silicon dioxide layer: 1 μm). Tapered DCs are used as TE 0 &TE 1 mode (de)multiplexers thanks to their simple structure and larger fabrication tolerance than normal DCs [7,20]. Fully etched apodized grating couplers [21] are used as input and output ports.…”