Fabrication Technique for Preparing Nanogap Electrodes by Conventional Silicon Processes

Hashioka, Shingi; Tsuritani, Hiroyuki; Obata, Tsutomu; Kadosaki, Masahiro; Fujiki, Satoshi; Tanino, Katsumi

doi:10.1143/jjap.44.4213

Cited by 5 publications

(4 citation statements)

References 7 publications

(7 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Therefore, recently, some non‐conventional techniques in combination with conventional photolithography have been proposed for the preparation of nanoelectrodes, nanogaps and other nano‐scaled devices. These techniques include, for instance, a photoresist thermal reflow and shrinking (Meng et al , 2001) or photoresist ashing technique (Kim et al , 2008), a shadow evaporation process (Ishida et al , 2005), a controlled size‐reduction using the oxidation of Si (Choi et al , 2003; Hashioka et al , 2005; Cho et al , 2007) or laser‐assisted electrochemical etching (Juhasz and Linnros, 2002), chemical‐mechanical polishing (Lee et al , 2003), the decrease of separation between metallic electrodes by means of an electro‐deposition from an electrolyte solution (Morpurgo et al , 1999), methods that utilize a sidewall structure (Chung et al , 2002), a self‐aligned plasma etching of a silicon dioxide layer and silicon substrate (Georgiev et al , 2003), or a lateral, partial anodic oxidation of the side‐edge of a photolithographically‐structured metallic film (e.g. Ti) (Hashioka et al , 2003), techniques that use a silicon‐on‐insulator structure (Strobel et al , 2007), etc.…”

Section: Introductionmentioning

confidence: 99%

Polysilicon nanogap fabrication using a thermal oxidation process

Dhahi

Hashim

Ali

et al. 2012

Microelectronics International

View full text Add to dashboard Cite

Purpose -Nanogap electrodes have important applications in power saving devices, electrochemical sensors and dielectric detections of biomolecules. The purpose of this paper is to report on the fabrication and characterization of polysilicon nanogap patterning using novelties technique. Design/methodology/approach -Polysilicon material is used to fabricate the nanogap structure and gold is used for the electrode and two chrome masks are used to complete this work; the first mask for the nanogap pattern and a second mask for the electrode. The method is based on the control of the coefficients (temperature and time) with an improved pattern size resolution thermal oxidation. Findings -Physical characterization by scanning electron microscopy (SEM) demonstrates such nanogap electrodes could be produced with high reproducibility and precision. Electrical characterization shows that nanogap enhanced the sensitivity of the device by increase the capacitance and the conductivity as well. They have also good efficiency of power consumption with high insulation properties. Originality/value -With this technique, there are no principal limitations to fabricating nanostructures with different layouts down to several different nanometer dimensions. The paper documents the fabrication of nanogaps electrodes on a polysilicon, using low-cost techniques such as vacuum deposition and conventional lithography. Polysilicon is a low-cost materials and has desirable properties for semiconductor applications. A method of preparing a nanogap electrode according to the present innovation has an advantage of providing active surface that can easily be modified for immobilizations of biomolecules.

show abstract

Section: Introductionmentioning

confidence: 99%

Polysilicon nanogap fabrication using a thermal oxidation process

Dhahi

Hashim

Ali

et al. 2012

Microelectronics International

View full text Add to dashboard Cite

show abstract

“…Recently, some non-conventional techniques in combination with conventional photolithography have been proposed for the preparation of nanoelectrodes, nanogaps and other nano-scaled devices. These techniques include, for instance, a photoresist thermal reflow and shrinking (Meng et al, 2001) or photoresist ashing technique (Kim et al, 2008), a shadow evaporation process (Ishida et al, 2005), a controlled size-reduction using the oxidation of Si (Choi et al, 2003;Hashioka et al, 2005;Cho et al, 2007) or laser-assisted electrochemical etching (Juhasz and Linnros, 2002), chemical-mechanical polishing (Lee et al, 2003), the decrease of separation between metallic electrodes by means of an electro-deposition from an electrolyte solution (Morpurgo et al, 1999), methods that utilize a sidewall structure (Chung et al, 2002), a selfaligned plasma etching of a silicon dioxide layer and silicon substrate (Georgiev et al, 2003), or a lateral, partial anodic oxidation of the side-edge of a photolithographically-structured metallic film (e.g., Ti) (Hashioka et al, 2003), and techniques that use a silicon-on-insulator structure (Strobel et al, 2007).…”

Section: Introductionmentioning

confidence: 99%

Fabrication of 6 nm gap on silicon substrate for power-saving appliances

Dhahi¹

2012

Int. J. Phys. Sci.

View full text Add to dashboard Cite

We document a thermal oxidation process for the reproducible fabrication of 6-nm gaps on silicon-oninsulator (SOI) substrate. Nanogaps sizes of this dimension are implicated to eliminate contributions from double-layer capacitance in the dielectric sensing of proteins or nucleic acids. The method combines conventional photolithography and pattern-size reduction technique to create a desired-size gap. The gaps are physically characterized with a field emission scanning electron microscopy (FESEM). Preliminary results show that gap-size reduction provides an improvement in conductivity, permittivity and capacitance parameters, reflecting the potential applications of the fabricated structures in low-power consuming electrical devices. The task is completed with two chrome masks: the first mask is for the nanogap pattern and the second one is for the electrodes. An improved resolution of pattern size is obtained by controlling the oxidation time of the final cycle. The reproducibility of the method is proven in triplicate experiments. We believe the method can be used in the industrial production of desired-size nanogaps on a variety of low-cost substrates.

show abstract

“…Therefore, recently, some non-conventional techniques in combination with conventional photolithography have been proposed for the preparation of nano-electrodes, nano-gaps and other nano-scaled devices. These techniques include, for instance, a photoresist thermal reflow and shrinking 18 or photoresist ashing technique, 19 a shadow evaporation process, 20 a controlled size-reduction using the oxidation of Si [21][22][23] or laserassisted electrochemical etching, 24 chemical-mechanical polishing, 25 the decrease of separation between metallic electrodes by means of an electro-deposition from an electrolyte solution, 26 methods that utilize a sidewall structure, 27 a self-aligned plasma etching of a silicon dioxide layer and silicon substrate, 28 or a lateral, partial anodic oxidation of the side-edge of a photolithographicallystructured metallic film (e.g., Ti), 29 techniques that use a silicon-on-insulator structure, 30 for the fabrication of self-aligned nanostructures by means of conventional photolithography combined with patternsize reduction techniques has recently been proposed by the authors. 31 32 The method was experimentally demonstrated by patterning nanostructures with different sizes and layouts on a Si substrate.…”

Section: Introductionmentioning

confidence: 99%

Fabrication and Characterization of 50 nm Silicon Nano-Gap Structures

Dhahi¹,

Hashim²,

Ahmed³

2011

sci adv mat

View full text Add to dashboard Cite

A simple method for the fabrication of nano-gaps less than 50 nm by using conventional photolithography combined with patterned-size reduction techniques is presented. Silicon material is used to fabricate the nano-gap structure and gold is used for the electrode. Two chrome masks are proposed to complete this work, the first mask for the nano-gap pattern and a second mask for the electrode. The method is based on the control of the coefficients (temperature and time) with an improved pattern size resolution by thermal oxidation. With this technique, there are no principal limitations to fabricating nanostructures with different layouts down to several nanometers in dimension. In this work, the proposed method is experimentally demonstrated by preparing the nano-gaps on a Si-SiO 2 substrate down to dimensions of 50 nm. The optical characterization that is applied to check the nano-gap structure is by using the scanning electron microscope (SEM).

show abstract

Fabrication Technique for Preparing Nanogap Electrodes by Conventional Silicon Processes

Cited by 5 publications

References 7 publications

Polysilicon nanogap fabrication using a thermal oxidation process

Polysilicon nanogap fabrication using a thermal oxidation process

Fabrication of 6 nm gap on silicon substrate for power-saving appliances

Fabrication and Characterization of 50 nm Silicon Nano-Gap Structures

Contact Info

Product

Resources

About