Fabrication Strategies of Metal–Ferroelectric–Insulator–Silicon Gate Stacks Using Ferroelectric Hf–Zr–O and High-k HfO₂ Insulator Layers for Securing Robust Ferroelectric Memory Characteristics

Abstract

Metal–ferroelectric–insulator–Si (MFIS) gate stack structures were fabricated and characterized to investigate the optimum process indicators when HfO2-based thin films were exploited as the ferroelectric layer (FL) for the ferroelectric-field-effect-driven nonvolatile memory operations. The interfacial transition layer thicknesses of the metal–insulator–semiconductor capacitors using high dielectric constant (high-k) insulator layers (ILs) were preliminarily examined to be approximately 0.7 and 0.5 nm for the Pt/HfO2/Si and Pt/Al2O3/Si capacitors, respectively, which corresponded to Hf silicate and amorphous SiO2. As the result, the introduction of HfO2 IL was verified to enhance the capacitance coupling ratio 1.7 times higher than that by the use of Al2O3 IL for the MFIS devices. Alternatively, among the fabricated MFIS capacitors with various combinations of high-k ILs and HfO2-based FLs, the counterclockwise hysteresis loops supported by ferroelectric field effects in the C–V curves were obtained only from the devices employing the HfZrO (HZO) FLs and HfO2 ILs. Especially, when the film thicknesses of the HZO FL and HfO2 IL were controlled to be 20 and 5 nm, respectively, the MFIS capacitor exhibited the ferroelectric memory window as large as 2.1 V and the long-term retention with a charge loss of only 11% after a lapse of time for 104 s. These differences in the device characteristics among the controlled devices originated from the combined effects of voltage distribution between the FLs and ILs, crystallinity of the FL prepared on various ILs, and capacitance coupling ratio, which could be suggested as important control parameters to optimize the memory operations of MFIS devices.

A perspective on the physical scaling down of hafnia-based ferroelectrics

“…In accordance with the surface energy model proposed by Park et al and Materlik et al [88,89], the tetragonal phase may be more likely to be stabilized as the thickness of the Hf 0.5 Zr 0.5 O 2 layer decreases, resulting in a more pronounced wake-up effect. In addition, the tetragonal phase of Hf 0.5 Zr 0.5 O 2 has been reported to exist locally at IL at 0.5 nm [140]. Thus, the appearance of the significant wake-up effect as the thickness of the Hf 0.5 Zr 0.5 O 2 layer decreases may be explained by the stabilization of the tetragonal phase and the increased proportion of the tetragonal phase present at IL as the thickness of the Hf 0.5 Zr 0.5 O 2 layer decreases.…”

Neuromorphic devices based on fluorite‐structured ferroelectrics

“…In contrast, FTJs are less sensitive to trapped charges during the readout process than FeFETs; however, similar reliability issues exist in FTJs based on ferroelectric/dielectric bilayers 191 . Several interfacial engineering methods, such as using a high‐k interlayer such as SiON, AlON, SiN x , ZrO 2 , Al 2 O 3 , or TiO 2 as the interlayer to replace SiO x , utilizing a scavenging layer, and optimizing annealing conditions, have been proposed to overcome these challenges, 27,124,125,169,192–203 and have showed impressive stability 96,99,192,204 . In addition to the properties related to device reliability, other key device performance parameters are scalability, switching speed, and programming energy.…”

“…AlON, SiN x , ZrO 2 , Al 2 O 3 , or TiO 2 as the interlayer to replace SiO x , utilizing a scavenging layer, and optimizing annealing conditions, have been proposed to overcome these challenges, 27,124,125,169,[192][193][194][195][196][197][198][199][200][201][202][203] and have showed impressive stability. 96,99,192,204 In addition to the properties related to device reliability, other key device performance parameters are scalability, switching speed, and programming energy.…”

Impact of HfO2 Dielectric Layer Placement in Hf0.5Zr0.5O2‐Based Ferroelectric Tunnel Junctions for Neuromorphic Applications

“…[ 37,38 ] Moreover, concerning device performance metrics such as higher remanent polarization (P r ), long‐term retention, ferroelectric memory window, and stability of the o‐phase, structures incorporating an additional insulator layer within the ferroelectric layer exhibit improved characteristics compared to those utilizing solely the ferroelectric layer. [ 39 − 42 ]…”