2020
DOI: 10.1115/1.4046848
|View full text |Cite
|
Sign up to set email alerts
|

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

Abstract: This work will specifically detail the development of a processing and fabrication route for a three-dimensional asynchronous field-programmable gate array (3D-AFPGA) design based on an extension of pre-existing two-dimensional-field-programmable gate array (2D-FPGA) tile designs. The periodic nature of FPGAs permits the use of an alternative approach, whereby the design entails splitting the FPGA design along tile borders and inserting through silicon vias (TSVs) at regular spatial intervals. This serves to e… Show more

Help me understand this report

Search citation statements

Order By: Relevance

Paper Sections

Select...

Citation Types

0
0
0

Publication Types

Select...

Relationship

0
0

Authors

Journals

citations
Cited by 0 publications
references
References 15 publications
0
0
0
Order By: Relevance

No citations

Set email alert for when this publication receives citations?