Fabrication Process for Josephson Integrated Circuits

Abstract

A process for fabricating experimental Josephson integrated circuits is described that is based primarily on the use of vacuum-deposited Pb-alloy and SiO films patterned by photoresist stencil lift-off. The process has evolved from one previously reported, with changes having occurred injunction electrodes, tunnel barrier formation, layer patterning, device geometry, and minimum linewidths. Films of Pb-In{l2 wt%)-Au(4 wt%) alloy (200-800 nm thick) are used for forming junction base electrodes, interferometer controls, and interconnection lines. Tunnel barriers are formed on the base electrode films by thermal oxidation and subsequent sputter-etching in an rf-oxygen plasma. Junction counter electrodes are formed from 400-nm-thick Pb-Bi(29 wt%) alloy films. Ground planes are formed from 300-nm-thick Nb films patterned by subtractive etching and insulated in part by a Nbfi. layer formed by liquid anodization. Films of the intermetallic compound Auln,^ (30-43 nm thick) are used for forming terminating, load, and damping resistors. The SiO films are used for interlayer insulation, for defining junction areas in interferometers, and as protective coatings. Layer patterning is achieved mainly by means of photoresist lift-off stencils. By utilizing this process, experimental logic and memory circuits containing =^100 interferometers with lines as small as 2.5 p-m in width have been successfully fabricated.

Fundamental Limits on Squid Technology

“…Experiments to observe quantum corrections to the noise in resistively shunted junctions have been carried out by Koch et al (198la, 1982 (Greiner et al, 1980). The configuration is shown in Fig.…”

Electron-Beam Resists for Lift-Off Processing with Potential Application to Josephson Integrated Circuits

“…Tests were made both on wafers coated with SiO and with Pb-In-Au alloy [13] (Mj layer) films, the types of surfaces found in Josephson circuits. The wafers were exposed with an electron dose of 1.5 x lO"* C/cm at 15 keV (2.4 x 10""" J) in a Vectorscan [22] exposure machine.…”

“…The chlorobenzene soak reduces the development rate near the resist surface and provides a reproducible undercut under a wide range of processing conditions. This approach has been used to develop a process for fabricating Josephson integrated circuits [13], We have attempted to improve the resolution of the process by substituting electron exposure for optical exposure. Our experience with ®AZ-1350J makes the use of the same resist for e-beam exposure very attractive, since this material is known to be suitable for all steps in the Josephson process.…”

“…Comparatively complex Josephson integrated circuits have been fabricated and shown to provide high switching speeds with low power dissipation [10,11]. The fabrication process consists of the evaporation and patterning of a number of thin film layers of superconductors, resistors, and insulators and the use of plasma cleaning and oxidation processes [12,13]. Patterning has generally been carried out using optical lithography with minimum feature sizes of about 2.5 /u.m.…”

Fabrication of Full High-TcSuperconducting YBa2Cu3O7-xTrilayer Junctions Using a Polishing Technique

“…Thus, we introduced a simple device structure, such as a Pb-alloy-based Josephson tunneling junction, 16) into YBCO/ PrBa 2 Cu 3 O 7Àx (PBCO)/YBCO trilayer junctions. In this device structure, the YBCO layer as a counter electrode serves as a wiring layer.…”