Fabrication of Single Crystal Silicon Nanowire Bridge

Park, Kyung Tea; Kim, Hyeon‐Cheol; Chun, Kukjin

doi:10.1109/sensordevices.2010.53

Cited by 2 publications

(9 citation statements)

References 6 publications

(6 reference statements)

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“…Originally developed for the fabrication of free-standing Si micromechanical structures within bulk Si substrates, [29][30][31][32][33][34][35] the technique was recently extended into the nanoscale. [36][37][38][39][40] Using a two-stage etching technique, NWs are obtained at the upper surface of the device layer, i.e., coplanar with the MEMS surface.…”

Section: Fabrication Techniquesmentioning

confidence: 99%

“…Si NWs with a critical dimension (CD) of 20 nm could be obtained after a 10 μm-deep etch step, thereby bridging a three-order-of-magnitude scale gap. [39,43] An array of such Si NWs fabricated within bulk Si is depicted in Figure 2a, where all features were monolithically machined from the same Si [36][37][38][39][40]47] Column (ii): Si NW fabrication in thin SOI with MEMS fabricated subsequently within a thick polySi layer. [18] Fabrication steps: a) patterning of etch mask by nanolithography, b) shallow Si etch to define NW partially in (i) and fully in (ii), c) passivation for protection against further Si etch, d) polySi growth in (ii) to fabricate MEMS device layer, e) deep Si etch for MEMS fabrication, and f ) release through BOX etching.…”

Section: Fabrication Techniquesmentioning

confidence: 99%

“…Its adaptation at the nanoscale as depicted in Figure 1, column (i), proved to enable monolithic cofabrication of the Si NWs. Si NWs with a critical dimension (CD) of 20 nm could be obtained after a 10 μm-deep etch step, thereby bridging [36][37][38][39][40]47] Column (ii): Si NW fabrication in thin SOI with MEMS fabricated subsequently within a thick polySi layer. [18] Fabrication steps: a) patterning of etch mask by nanolithography, b) shallow Si etch to define NW partially in (i) and fully in (ii), c) passivation for protection against further Si etch, d) polySi growth in (ii) to fabricate MEMS device layer, e) deep Si etch for MEMS fabrication, and f ) release through BOX etching.…”

Section: Fabrication Techniquesmentioning

confidence: 99%

“…Column (i): An adaptation of the SCREAM process in thick SOI incorporating a two‐stage etch technology and sidewall passivation. [ 36–40,47 ] Column (ii): Si NW fabrication in thin SOI with MEMS fabricated subsequently within a thick polySi layer. [ 18 ] Fabrication steps: a) patterning of etch mask by nanolithography, b) shallow Si etch to define NW partially in (i) and fully in (ii), c) passivation for protection against further Si etch, d) polySi growth in (ii) to fabricate MEMS device layer, e) deep Si etch for MEMS fabrication, and f) release through BOX etching.…”

Section: Fabrication Techniquesmentioning

confidence: 99%

“…Figure 1. Column (i): An adaptation of the SCREAM process in thick SOI incorporating a two-stage etch technology and sidewall passivation [36][37][38][39][40]47]. Column (ii): Si NW fabrication in thin SOI with MEMS fabricated subsequently within a thick polySi layer [18].…”

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confidence: 99%

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Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

et al. 2023

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The miniaturization of microelectromechanical systems (MEMS) physical sensors is driven by global connectivity needs and is closely linked to emerging digital technologies and the Internet of Things. Strong technical advantages of miniaturization such as improved sensitivity, functionality, and power consumption are accompanied by significant economic benefits due to semiconductor manufacturing. Hence, the trend to produce smaller sensors and their driving force resemble very much those of the miniaturization of integrated circuits (ICs) as described by Moore's law. In this respect, with its IC‐, and MEMS‐compatibility, and scalability, the silicon nanowire is frequently employed in frontier research as the sensor building block replacing conventional sensors. The integration of the silicon nanowire with MEMS has thus generated a multiscale hybrid architecture, where the silicon nanowire serves as the piezoresistive transducer and MEMS provide an interface with external forces, such as inertial or magnetic. This approach has been reported for almost all physical sensor types over the last decade. These sensors are reviewed here with detailed classification. In each case, associated technological challenges and comparisons with conventional counterparts are provided. Future directions and opportunities are highlighted.

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Section: Fabrication Techniquesmentioning

confidence: 99%

Section: Fabrication Techniquesmentioning

confidence: 99%

Section: Fabrication Techniquesmentioning

confidence: 99%

Section: Fabrication Techniquesmentioning

confidence: 99%

mentioning

confidence: 99%

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Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

et al. 2023

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Simplified top-down fabrication of sub-micron silicon nanowires

Zare Pakzad,

Akinci,

Karimzadehkhouei

et al. 2023

Semicond. Sci. Technol.

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Silicon nanowires are among the most promising nanotechnology building blocks in innovative devices with numerous applications as nanoelectromechanical systems. Downscaling the physical size of these devices and optimization of material functionalities by engineering their structure are two promising strategies for further enhancement of their performance for integrated circuits and future-generation sensors and actuators. Integration of silicon nanowires as transduction elements for inertial sensor applications is one prominent example for an intelligent combination of such building blocks for multiple functionalities within a single sensor. Currently, the efforts in this field are marred by the lack of batch fabrication techniques compatible with semiconductor manufacturing. Development of new fabrication techniques for such one-dimensional structures will eliminate the drawbacks associated with assembly issues. The current study aims to explore the limits of batch fabrication for a single nanowire within a thick Si layer. The objective of the current work goes beyond the state of the art with significant improvements to the recent viable approach on the monolithic fabrication of nanowires, which was based on a conformal side-wall coating for the protection of the nanoscale silicon line followed by deep etch of the substrate transforming the protected layer into a silicon nanowire. The newly developed fabrication approach eliminates side wall protection and thereby reduces both process complexity and process temperature. The technique yields promising results with possible improvements for future micro and nanofabrication processes.

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Fabrication of Single Crystal Silicon Nanowire Bridge

Cited by 2 publications

References 6 publications

Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

Silicon Nanowires Driving Miniaturization of Microelectromechanical Systems Physical Sensors: A Review

Simplified top-down fabrication of sub-micron silicon nanowires

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