Fabrication of micron size Nb/Al-Al/sub 2/O/sub 3//Nb junctions with a trilevel resist liftoff process

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Fig. 1. An etched trilayer/Cr-Au test junction under a quadlevel resist structure before SiO deposition is shown. It can be seen that the SF6+CHF3-based Nb etch is anisotropic. The Cr-Au button is clearly seen to be defined by the NFR resist and not the trilevel resist Nb (which defines the Nb junction size). Abstract)) ))We have found the use of a Ga+ based focused ion beam (FIB) system to be very useful in characterizing our superconducting-insulating-superconducting (SIS) fabrication process. This tool enables us to physically carve cross sections in any feature of interest on our wafer which we can then image with an SEM. This process is used to examine and monitor improvements in the coverage of metalization layers over different circuit topography and in the critical "sealing" capabilities of our SiO insulation layer around the perimeter of the Nb junction counter electrode. It has also been used to better establish a submerged trilayer deposition process where the base electrode is imbedded in the quartz substrate. We have also improved our characterization of the tunnel barrier critical current density of our Nb/Al-oxide/Nb trilayer material by obtaining more accurate diameter measurements from FIB sectioned junctions. Index Items)) ))characterization, critical current density, cross section, and focused ion beam.

Section: Methodsmentioning

confidence: 99%

Use of a focused ion beam for characterizing SIS circuits

Bass

Clark

Zhang

et al. 2001

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“…We previously developed the first reported multi resist self-aligned junction insulation process [9], [10] for SIS junctions using a trilevel resist scheme. Multi-layer resists typically are composed of thick bottom organic "planarization" layer(s), a thinner inorganic 'barrier' layer(s) and a top imaging layer of photoresist.…”

Section: Introductionmentioning

confidence: 99%

Pentalevel Resist Process for the Precise Fabrication of Small Area SIS Junctions

Lichtenberger

Stronko

Wang

et al. 2009

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We have fabricated high quality M1/barrier/M2/Au superconducting insulating superconducting (SIS) junctions with Au over-layers using a new multilayer pentalevel resist process. The wafer NFR polyimide SiO 2 Cr imaging resist pentalevel structure enables precise definition of submicron junction features in a self-aligned insulation process. This scheme, unlike our previous multilevel resists, affords precise definition of the final Nb layer from an initial etch of a thinner top Cr layer. The Cr layer, defined with chlorine based RIE, serves as an excellent mask for the subsequent fluorine and oxygen based RIE etches of the remaining pentalevel stack and M2 electrode. We present a detailed description of the pentalevel process and electrical characteristics of NbTiN SIS junctions fabricated with this new technique.

“…The greatest challenge in this process typically centers on the development of a working junction resist scheme that permits both precise definition and control of junction area and also permits liftoff of a junction insulation layer that will protect the base electrode from the subsequent wiring/interconnection layer. Manuscript We developed the first trilevel resist scheme for a self-aligned SIS junction insulation process [8], [9]. Trilevel resists typically are composed of a thicker bottom organic planarization layer, a thinner inorganic 'barrier' and a top imaging layer of photoresist.…”

Section: Introductionmentioning

confidence: 99%

Ti quadlevel resist process for the fabrication of Nb SIS junctions

Clark

Zhang

Lichtenberger

2003

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We have fabricated high quality Nb/Al-oxide/Nb Superconductor-Insulator-Superconductor (SIS) junctions using a Ti-based quadlevel resist process. The quadlevel materials have been carefully chosen to optimize the fluorine-based anisotropic reactive ion etching of Nb and subsequent insulation coverage of the junctions in a self-aligned process. This SIS fabrication process enables excellent control of junction size and is also compatible with Au overlayer junction and junction anodization approaches.