Fabrication of High-Performance Bridged-Grain Polycrystalline Silicon TFTs by Laser Interference Lithography

Deng, Sunbin; Chen, Rongsheng; Zhou, Wei; Ho, J.; Wong, Man; Kwok, Hoi‐Sing

doi:10.1109/ted.2016.2520081

Cited by 11 publications

(14 citation statements)

References 11 publications

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cost. These previous results [11][12][13][14][15][16] reveal that the BG TFTs are promising for advanced AM and SoP applications. In a BG TFT, the channel is divided into several segments and bridged by submicron-scale heavily doped regions, which are called BG lines.

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mentioning

confidence: 54%

“…Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization. Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization.…”

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confidence: 99%

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High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

Zhang

Lin

Deng

et al. 2019

Adv Elect Materials

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cost. Recently, bridged-grain (BG) technique [11][12][13][14][15][16] has been proposed to improve device performance and reliability in poly-Si TFTs without increasing the thermal budget of crystallization. In a BG TFT, the channel is divided into several segments and bridged by submicron-scale heavily doped regions, which are called BG lines. Field effect mobility, on-state current (I on ), and threshold voltage (V th ) can be greatly enhanced, enlarged, and reduced due to the short channel effect and the reduced number of grain boundaries inside the channel. Meanwhile, the leakage current and kink effect are suppressed and decreased due to the drain electric field lowering. These previous results [11][12][13][14][15][16] reveal that the BG TFTs are promising for advanced AM and SoP applications. However, compared with the normal top-gate TFT process, the fabrication of BG TFTs involves one extra ion implantation process to form the doped periodical BG regions using a grating structure as a mask. The source/drain (S/D) doping is realized separately through another self-aligned ion implantation process using the gate layer as the mask. The dual implantation processes increase the complexity and cost of the device fabrication. Moreover, in both normal top-gate TFT process and BG TFT process, the dopant activation condition is limited by the metal gate electrodes. Taking Al for By utilizing anisotropic conductivity of bridged-grain (BG) lines, a polycrystalline silicon (poly-Si) thin-film transistor (TFT) without source/drain (S/D) doping is designed, simulated, and fabricated. In the new design, the current is made to flow along the BG lines in the S/D region and flow perpendicularly to the BG lines in the channel. By taking advantage of the anisotropic conductivity of the BG lines, the S/D doping process is eliminated and the fabrication process cost is reduced. Meanwhile, the advantages of adopting BG lines are maintained. The as-fabricated TFTs without S/D doping exhibit excellent device characteristics, compared with normal TFTs. The reliability of TFTs without S/D doping is also evaluated under hot carrier stress and negative/positive bias stress. Additionally, the proposed new TFT structure allows a wider range of dopant activation conditions.

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confidence: 54%

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confidence: 99%

High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

Zhang

Lin

Deng

et al. 2019

Adv Elect Materials

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“…BG structure [9]- [13] has been successfully applied to smallgrain poly-Si TFTs to improve device characteristics. Besides the Ion improvement due to short channel effect and grain size effect, BG structure can effectively to suppress Ioff by electric field reduction at the drain side due to the multi-junction effect.…”

Section: Bg µC -Si Tftmentioning

confidence: 99%

“…The µFE of the BG self-aligned top-gate µc -Si TFTs is 19.2 cm 2 /Vs and the effective µFE is around 9.6 cm 2 /Vs. However, the degree of characteristic improvements from BG structure in self-aligned top-gate µc -Si TFTs is not as good as that obtained from the BG structure in self-aligned top-gate poly-Si TFTs [9]- [13]. This may be due to the incomplete process optimization.…”

Section: Bg µC -Si Tftmentioning

confidence: 99%

P‐1.9: Characterization of Self‐Aligned Top‐Gate Microcrystalline Silicon Thin Film Transistors

Zhang

Yan

Deng

et al. 2018

Symp Digest of Tech Papers

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Self‐aligned top‐gate microcrystalline silicon (µc‐Si) thin film transistors (TFTs) are fabricated and characterized. By replacing high‐temperature SiO2 with low‐temperature SiO2, the performance of self‐aligned top‐gate µc‐Si TFTs can be greatly improved due to the prevention of hydrogen diffusion into the air. The bridged grain (BG) structure is successfully applied to self‐aligned top‐gate µc‐Si TFTs for the first time. By employing the BG doping inside the channel, all device characteristics are improved in self‐aligned top‐gate µc‐Si TFTs.

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“…Compared with other LTPS technologies, such as solid-phase crystallization (SPC) [8] and metal-induced crystallization (MIC) [9], ELA is quite mature and gives better electrical characteristics and better reliability. Instead of laser interference photolithography or nanoimprinting technology [10] [11], we chose the photo-mask for exposure to build the BG structure which can accommodate industry manufacture. Compared with the device with a separate BG structure or a separate LDD structure, the device with both BG and LDD structures behaves better electrical characteristic.…”

Section: Introductionmentioning

confidence: 99%

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

Guo

Yan

et al. 2019

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We lead the lightly doped drain (LDD) structure into the bridged‐grain (BG) poly‐Si thin film transistor (TFT). This combined structure can restrain the gate induced drain leakage current (GIDL) and the electrical characteristics shows not much sacrifice. A high Ion/Ioff current ratio 3.79×108 is achieved. Besides, the device reliability is improved significantly. Because the lateral electrical field decreases by LDD, lower trap state density is generated in the SiO2/poly‐Si interface and the grain boundaries of poly‐Si near the surface conduction channel, resulting in the stable on‐state drive current (Ion) and drain saturation voltage (Vdsat). All test results indicate that the BG poly‐Si TFT with a LDD structure will work well and has a great potential for system‐on‐panel application.

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Fabrication of High-Performance Bridged-Grain Polycrystalline Silicon TFTs by Laser Interference Lithography

Cited by 11 publications

References 11 publications

High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

High‐Performance Polycrystalline Silicon Thin‐Film Transistors without Source/Drain Doping by Utilizing Anisotropic Conductivity of Bridged‐Grain Lines

P‐1.9: Characterization of Self‐Aligned Top‐Gate Microcrystalline Silicon Thin Film Transistors

P‐6.6: Effects of lightly Doped Drain Structure in n‐channel ELA Bridged‐Grain Poly‐Si TFTs

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