Fabrication of arrays of large step-free regions on Si(001)

Abstract

In this letter we describe a method for producing large areas of Si(001) surfaces which are (i) free of atomic steps and (ii) arranged in regular patterns on the wafer. The first step is the fabrication of a two-dimensional grating structure using e-beam lithography and reactive ion etching. This grating is then annealed within the appropriate temperature window in ultrahigh vacuum to produce the desired array of (001) step-free regions. We illustrate the success of the method through the use of low-energy electron microscopy for a few repeat spacings on test structures each extending over a 3×3 mm2 area. Alternative processing steps are discussed as well as application to submicron device technology.

Self-assembly of defect-free nanostripe arrays on B-doped Si(001)

“…Pit widths larger than ~10 μm were not used, owing to vacancy island formation prior to the full expansion of the existing vacancy island. 13,16 The high LEEM contrast ratio between surfaces separated by single atomic steps is due to the 90° degree rotation of the electron diffraction patterns of alternating Si dimer rows. 10 A slightly tilted (0,0) beam (bright field) was used for imaging.…”

“…To overcome this limitation, Tanaka et al proposed a method of creating large step-free regions on Si(001) via etching an array of pits onto the surface, and heating to high temperature in ultrahigh vacuum (UHV). 13 This causes the formation and successive expansion of oval vacancy islands at pit bottoms, eventually creating large step-free terraces. Nielsen et al used such patterned surfaces to create extended stripe arrays by Si and B 2 H 6 co-deposition.…”

Simulations of denuded-zone formation during growth on surfaces with anisotropic diffusion

“…The model is designed to closely match the experimental conditions of high-temperature (530-700°C) nucleation and growth studied by Nielsen et al, 11 who used low-energy electron microscopy ͑LEEM͒ to observe Si island nucleation on large (Ͼ5 m) step-free Si(001)-(2ϫ1) terraces prepared by the method proposed by Tanaka et al 15 A primary difference in the studies of Nielsen et al from previous LEEM studies of Si island coarsening by Bartelt et al 16 is that Nielsen and co-workers observed nucleation and growth at constant temperature, whereas Bartelt and co-workers deposited Si at room temperature followed by coarsening at higher temperature (670°C). Figure 10 shows a typical nucleation sequence on a ϳ5 mϫ6 m rectangular terrace measured at 560°C and using a Si deposition flux of 0.2 ML/min.…”

Preparing arrays of large atomically flat regions on single crystal substrates

“…Several groups have reported success in producing arrays of atomically flat regions on semiconductors [10][11][12] as well as on oxides [13] by patterning the substrates prior to final cleaning and annealing procedures. In these processes, lithographically produced trenches or mounds are used as efficient sinks for surface steps that become mobile during annealing.…”