Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Suzuki, Daisuke; Natsui, Masanori; Mochizuki, Ayako; Honjo, H.; Sato, Hideo; Fukami, Shunsuke; Ikeda, Shoji; Endoh, Tetsuo; Ohno, Hideo; Hanyu, Takahiro

doi:10.1109/vlsit.2015.7223644

Cited by 15 publications

(16 citation statements)

References 2 publications

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“…It should be noted that [22] proposes an NVM-LUT based structure but lacks an NVM based SB. In addition, the study in [38] proposed a design based on NVM-SB. Therefore from the overall comparison, we assume that there is a lack of circuit-based SRAM-based design.…”

Section: F Performance Analysis Efficient Programming Circuit With Rmentioning

confidence: 99%

Comprehensive Examination on Resistive Random Access Memory

Dharani*,

Bhavani,

Hridhya

2019

IJRTE

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With the latest advances in materials science, resistive random access memory (RRAM) devices are attracting non-volatile, low power consumption, non-destructive read, and high density memory. Related performance parameters for RRAM devices include operating voltage, operating speed, resistivity, durability, retention time, device yield, and multi-level storage. Numerous resistive mechanisms, such as conductive filaments, space charge limited conduction, trap charging and discharging, Schottky emission, and pool-Frenkel emission, have been proposed to explain the resistance switches of RRAM devices. Therefore, in this work, different oxide-based random access memories (RRAMs) were provided for comprehensive investigation of neuromorphiccalculations. With the development of RRAM, the physical mechanism of conduction, the basic history of neuromorphic calculations begins. Finally, suggestions for future research, as well as waiting for the challenges of RRAM equipment, are given.

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Section: F Performance Analysis Efficient Programming Circuit With Rmentioning

confidence: 99%

Comprehensive Examination on Resistive Random Access Memory

Dharani*,

Bhavani,

Hridhya

2019

IJRTE

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“…The tile is composed of a power switch, a configurable logic block (CLB), a switch block (SB), and two connection blocks (CBs). MTJ devices are stacked over the CMOS circuit plane of each block [6]. When the selftermination signal becomes high, the power switch of the tile is turned off.…”

Section: Proposedmentioning

confidence: 99%

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Suzuki

Hanyu

2017

IEICE Trans. Inf. & Syst.

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SUMMARYAn energy-efficient nonvolatile FPGA with assuring highly-reliable backup operation using a self-terminated power-gating scheme is proposed. Since the write current is automatically cut off just after the temporal data in the flip-flop is successfully backed up in the nonvolatile device, the amount of write energy can be minimized with no write failure. Moreover, when the backup operation in a particular cluster is completed, power supply of the cluster is immediately turned off, which minimizes standby energy due to leakage current. In fact, the total amount of energy consumption during the backup operation is reduced by 66% in comparison with that of a conventional worst-case-based approach where the long time write current pulse is used for the reliable write. key words: field-programmable gate array (FPGA), power gating, magnetic tunnel junction (MTJ) device, and low power digital

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“…2) By replacing volatile working memories such as static random access memories (SRAMs) and dynamic random access memories (DRAMs) by nonvolatile spintronics-based ones, i.e., magnetoresistive random access memories (MRAMs), one can drastically reduce the power consumption of ICs while maintaining high performance as was demonstrated in recent studies. [3][4][5][6][7][8] Spintronics memory devices can be classified into two categories according to their structure: two-and three-terminal devices. Both devices generally include a magnetic tunnel junction (MTJ), and the read operation is performed using the tunnel magnetoresistance (TMR) effect.…”

Section: Introductionmentioning

confidence: 99%

Magnetization switching schemes for nanoscale three-terminal spintronics devices

Fukami

Ohno

2017

Jpn. J. Appl. Phys.

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Utilizing spintronics-based nonvolatile memories in integrated circuits offers a promising approach to realize ultralow-power and high-performance electronics. While two-terminal devices with spin-transfer torque switching have been extensively developed nowadays, there has been a growing interest in devices with a three-terminal structure. Of primary importance for applications is the efficient manipulation of magnetization, corresponding to information writing, in nanoscale devices. Here we review the studies of current-induced domain wall motion and spin-orbit torque-induced switching, which can be applied to the write operation of nanoscale three-terminal spintronics devices. For domain wall motion, the size dependence of device properties down to less than 20 nm will be shown and the underlying mechanism behind the results will be discussed. For spin-orbit torque-induced switching, factors governing the threshold current density and strategies to reduce it will be discussed. A proof-ofconcept demonstration of artificial intelligence using an analog spin-orbit torque device will also be reviewed.

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Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure

Cited by 15 publications

References 2 publications

Comprehensive Examination on Resistive Random Access Memory

Comprehensive Examination on Resistive Random Access Memory

Energy-Efficient and Highly-Reliable Nonvolatile FPGA Using Self-Terminated Power-Gating Scheme

Magnetization switching schemes for nanoscale three-terminal spintronics devices

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