Nanoelectronic field-effect devices fabricated with 1-integration of nanowire devices. Low temperature synthesis is D semiconductor nanowires synthesized by bottom-up techniques preferred because it helps reducing growth defects, preventing are likely among those immediate successors of the top-down deformation, and minimizing dopant diffusion where local silicon CMOS technology, preserving the spirit of Moore's Law.doping is highly demanded in nanolectronic device design.The nanotechnology-embedded chip technology may emerge in the foreseeable future. However, there exists a gap betwveen synthesis research and industrial application. Some of the critical integration issues need to be addressed before nanowire-based chip technology becomes truly impacting. In this paper, efforts are made in directing nanowire synthesis towards realistic implementation in future miniaturized chip. The research work include i) low-temperature and high-yield Ge nanowire synthesis, ii) Ge nanowires-on-insulator (GeNOI, iii) industry-benign metal cata ysts, and iv) Ge quantum-wires synthesis.