Fabrication and characterization of an InAlAs/InGaAs/InP ring oscillator using integrated enhancement- and depletion-mode high-electron mobility transistors

Abstract

The fabrication and characterization of an 11-stage ring oscillator utilizing integrated enhancement-and depletionmode (E/D-mode) high-electron mobility transistors (HEMT's) in the lattice-matched InAlAs/InGaAs/InGaAs material system is demonstrated. The 0.5-m gate length depletion-mode HEMT's (D-HEMT's) used in the circuit exhibit a threshold voltage (V V V T T T ) of 0365 mV with a standard deviation of 19 mV, while the enhancement-mode HEMT's (E-HEMT's) with identical gate length display a V V V T T T of 195 mV with a standard deviation of only 9 mV. The unity current gain cutoff frequency (f f f t t t ) for both devices is 70 GHz. The extremely high uniformity of the threshold voltages of these devices allowed for the implementation of a ring oscillator utilizing direct coupled FET logic (DCFL). At a supply voltage of 0.4 V, a room temperature propagation delay time ( pd ) of 22.4 ps/stage, and a corresponding power dissipation of 120 W/stage is measured, yielding a power delay product (PDP) of 2.65 fJ/stage. To the best of the authors' knowledge, this is the first demonstration of a circuit employing E/D-HEMT technology in the lattice-matched InP-based material system.

Depletion-mode and enhancement-mode InGaP/GaAs -HEMTs for low supply-voltage applications

“…In logic circuit applications, high electron-mobility transistors (HEMTs) [1] and field-effect transistors (FETs) [2] provide excellent figures of merit in LSI-level complexity. Recently, extensive research has been focused upon HEMTs with reduced current-saturation voltages, which are suitable for low supply-voltage applications by implementing directcoupled FET logic (DCFL) technology [3][4][5][6]. The DCFL configuration composed of both enhancement-mode (E-mode) and depletion-mode (D-mode) FETs offers many advantages over other logic family members such as buffered FET logic (BFL), source coupled FET logic (SCFL), etc [5,6].…”

200°C/5 MHz GaN‐based gate driver circuits with 1 nF/4.7 Ω RC load for high‐temperature high‐frequency all‐GaN IC applications

“…The inverter's threshold voltage ( V TH ) is 1.8 V. The high‐ and low‐output logic levels ( V OH and V OL ) are 4 and 0.16 V, respectively, yielding a logic voltage swing of 3.84 V. The static logic‐low noise margin (NM L ) and logic‐high noise margin (NM H ) are 1.55 and 2.18 V. Large voltage swing and noise margins are desirable for all‐GaN IC applications. The logic‐low and logic‐high margins are defined using the method of largest width [6 ].…”

A low-power subharmonic injection-locked oscillator using E/D-mode GaAs PHEMTs for Ka-band applications

“…The E/D-mode (Enhanced and Depletion) GaAs PHEMT technique has been developed for high-speed digital or high-frequency rf communications [1][2][3][4]. Owing to the different threshold voltages of the D-mode and the Emode devices, the circuit complexity and the power consumption can be improved significantly as compared to the conventional D-mode design.…”