Extremely foldable LTPS TFT backplane using blue laser annealing for low‐cost manufacturing of rollable and foldable AMOLED display

Abstract

The crystallization of a-Si by blue laser annealing (BLA) is introduced for low-cost, high-resolution thin-film transistor (TFT) backplanes for foldable and rollable AMOLED displays. A big advantage of BLA is to provide low-temperature polycrystalline silicon (LTPS) with protrusion-free active channel. The BLA LTPS TFT manufactured on flexible substrate exhibits high field-effect mobility of 169 cm 2 /Vs, a smaller subthreshold voltage swing less than 201 mV/dec, and excellent electrical stability and mechanical robustness.blue laser annealing (BLA), flexible, foldable, low-temperature polycrystalline silicon (LTPS), thin-film transistor (TFT)

Poly‐Si Thin‐Film Transistors on Polyimide Substrate for 1 mm Diameter Rollable Active‐Matrix Organic Light‐Emitting Diode Display

“…The CNT/ GO mixed layer was formed on carrier glass by spray coating for mechanical detach. [18,19,[34][35][36] The PI was spin-coated to the thickness of 10 μm and then cured at %470 C for 2 h. After forming PI film on CNT/GO backbone on the carrier glass, a multilayer stack (five layers) of silicon dioxide (SiO 2 ) and silicon nitride (SiN x ), 25 nm each, was formed with 125 nm total thickness as a gas barrier by PECVD at 380 C. [19,34,35] A 400 nm-thick SiO 2 buffer layer was deposited on the gas barrier by PECVD at 380 C. Then, a 50 nm-thick hydrogenated amorphous-Si (a-Si:H) film was deposited by PECVD at 360 C and dehydrogenation was carried out in the furnace at 450 C for 2 h. The a-Si was crystallized to poly-Si by excimer laser annealing (ELA) using 308 nm UV laser. Then, a 100 nm SiO 2 was deposited as a GI by PECVD at 380 C and a 200 nm molybdenum (Mo) layer was deposited by sputtering as a gate metal.…”

“…After the complete fabrication process, the LTPS TFTs on PI substrate were detached from the carrier glass using a mechanical roller. [35][36][37] Electrical Measurements: The transfer (I DS ÀV GS ) characteristics of the TFTs were measured in dark at room temperature by an Agilent 4156C semiconductor parameter analyzer. The threshold voltage (V TH ) was defined as the V GS corresponding to I DS ¼ W/L Â 10 pA.…”

“…The TFT with an organic ITL used 1 μm PI layer by spin coating on the poly-Si directly. The PI layer was cured and annealed at 450 o C in a furnace for 2 h. [35][36][37][38][39] The via holes were formed by dry etching for source/drain contacts. Then, a 200 nm Mo was deposited and patterned as the source/ drain electrodes.…”

“…The CNT/ GO mixed layer was formed on carrier glass by spray coating for mechanical detach. [ 18,19,34–36 ] The PI was spin‐coated to the thickness of 10 μm and then cured at ≈470 °C for 2 h. After forming PI film on CNT/GO backbone on the carrier glass, a multilayer stack (five layers) of silicon dioxide (SiO 2 ) and silicon nitride (SiN x ), 25 nm each, was formed with 125 nm total thickness as a gas barrier by PECVD at 380 °C. [ 19,34,35 ] A 400 nm‐thick SiO 2 buffer layer was deposited on the gas barrier by PECVD at 380 °C.…”

“…After the complete fabrication process, the LTPS TFTs on PI substrate were detached from the carrier glass using a mechanical roller. [ 35–37 ]…”