The role of surface contamination, along with surface oxygen vacancies, plays a key role in the overall carrier transport in thin-film transistors (TFTs). In this study, it is shown that the quality of the semiconductor/dielectric interface and the surface roughness of the channel can be improved by O 2 annealing of the TiO 2 channel and subsequent N 2 O treatment. It has been observed that the surface contamination related to carbonaceous compounds by O 2 annealing at 500 °C (sample C500) is substantially reduced by 61% in comparison to that annealed at 375 °C (sample C375), which leads to a reduction of interface state traps (D it ) at the channel/dielectric interface. TFTs with a higher O 2 annealing temperature (C500) exhibit an SS of 88 mV/dec, an I ON /I OFF of ∼10 9 , and a mobility μ FE of 1.5 cm 2 /V-s under a battery-powered voltage of 1 V. In contrast, the sample C375 results in greater donor states such as surface oxygen vacancies (V o s), and the transistors exhibit a mobility μ FE of 2.95 cm 2 /V-s and an I ON / I OFF of ∼10 9 , despite a degradation of the SS value (123 mV/dec) due to the large number of interface states. Therefore, to fabricate high-performance devices, it is possible to tune the optimum values of surface contamination and oxygen vacancies by adjusting the O 2 annealing temperature. Also, these TFTs show excellent stability under both negative bias stress (NBS) and positive gate bias stress (PBS) in the dark as well as with laser illumination with minimal modifications of the electrical characteristics upon both gate stresses up to 1800 s, suggesting the feasibility of our TiO 2 TFTs for practical applications. A low gate leakage and I OFF current, as well as high-performance electrical characteristics, make the ICs ideal for low-power internet of things (IoT) applications.