Extraction based verification method for off the shelf integrated circuits

Saab, D.G.; Nagubadi, Vivek; Kocan, Fatih; Abraham, Jacob A.

doi:10.1109/asqed.2009.5206228

Cited by 9 publications

(7 citation statements)

References 8 publications

(8 reference statements)

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“…Another approach is to reverse engineer a netlist from a packaged IC using IC specification and scan operations [10]. The circuit connectivity is discovered by generating a set of tests that detect specific input/output dependencies existing in the specification.…”

Section: Related Workmentioning

confidence: 99%

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Expert System Simulation of Hardware

Leinweber

Singh

Papachristou

2013

2013 IEEE 25th International Conference on Tools With Artificial Intelligence

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Hardware lint tools based on static analysis techniques only check for structural, coding and consistency problems in RTL code. They have the limitation that they do not perform behavioral analysis and have a predefined rule-base that is not enhanced by users to capture human expertise. We present RTL-CLIPS, an RTL simulation environment based on CLIPS, an open-source expert system shell. In our approach, we do a semantically equivalent translation of RTL code into CLIPS facts. The simulator can be used by an heuristic rulebase to perform dynamic analysis of RTL code. Our method can better approximate design behavior by augmenting the pattern-matching capability of the CLIPS expert system with an environment for RTL simulation. We demonstrate our approach by analyzing ITC99 benchmark circuits. We discuss how our approach supports the reverse engineering of design behavior from RTL code.

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Section: Related Workmentioning

confidence: 99%

“…The design process begins with a specification and is successively refined to an implementable design. Reverse engineering is a process of back-tracing an implementation to its functional specification [6] [10] [7]. The combination of dynamic and static analysis techniques can better approximate the design behavior.…”

Section: Introductionmentioning

confidence: 99%

Expert System Simulation of Hardware

Leinweber

Singh

Papachristou

2013

2013 IEEE 25th International Conference on Tools With Artificial Intelligence

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“…On the other hand, some functional RE approaches have been investigated in recent years, e.g. [6] and [7]. Yet the complexity of logic testing approaches increases dramatically with the circuit size, especially in absence of full-scan testability in the design.…”

Section: Introductionmentioning

confidence: 99%

SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation

Wang

Narasimhan

Krishna

et al. 2012

2012 25th International Conference on VLSI Design

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Reverse Engineering (RE) has been historically considered as a powerful approach to understand electronic hardware in order to gain competitive intelligence or accomplish piracy. In recent years, it has also been looked at as a way to authenticate hardware intellectual properties in the court of law. In this paper, we propose a beneficial role of RE in post-silicon validation of integrated circuits (IC) with respect to IC functionality, reliability and integrity. Unlike traditional destructive RE approaches, we propose a fast non-destructive side-channel analysis approach that can hierarchically extract structural information from an IC through its transient current signature. Such a top-down side-channel analysis approach is capable of reliably identifying pipeline stages and functional blocks. It is also suitable to distinguish sequential elements from combinational gates. For extraction of random logic structures (e.g. control blocks and finite state machines) we combine side-channel analysis with logic testing based Boolean function extraction. The proposed approach is amenable to automation, scalable, and can be applied as part of post-silicon validation process to verify that each IC implements exclusively the functionality described in the specification and is free from malicious modification or Trojan attacks. Simulation results on a pipelined DLX processor demonstrate the effectiveness of the proposed approach.

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“…Even more recently, reverse engineering started to attract rapidly growing interest from academic community [41].…”

Section: Related Efforts and State-of-the-artmentioning

confidence: 99%

Securing netlist-level FPGA design through exploiting process variation and degradation

Zheng

Potkonjak

2012

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays

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The continuously widening gap between the Non-Recurring Engineering (NRE) and Recurring Engineering (RE) costs of producing Integrated Circuit (IC) products in the past few decades gives high incentives to unauthorized cloning and reverse-engineering of ICs. Existing IC Digital Rights Management (DRM) schemes often demands high overhead in area, power, and performance, or require non-volatile storage. Our goal is to develop a novel Intellectual Property (IP) protection technique that offers universal protection to both Application-Specific Integrated Circuits (ASIC) and Field-Programmable Gate-Arrays (FPGAs) from unauthorized manufacturing and reverse engineering. In this paper we show a proof-of-concept implementation of the basic elements of the technique, as well as a case study of applying the anti-cloning technique to a nontrivial FPGA design.

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Extraction based verification method for off the shelf integrated circuits

Cited by 9 publications

References 8 publications

Expert System Simulation of Hardware

Expert System Simulation of Hardware

SCARE: Side-Channel Analysis Based Reverse Engineering for Post-Silicon Validation

Securing netlist-level FPGA design through exploiting process variation and degradation

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