Extracting simple but accurate RC models for VLSI interconnect

Genderen, A.J. van; Meijs, N.P. van der

doi:10.1109/iscas.1988.15415

Cited by 21 publications

(19 citation statements)

References 8 publications

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“…[2,3], that the scanline based frontal elimination scheme provides a reasonably good ordering scheme. This is in fact an implicit ordering scheme, since it is determined by the scanline direction and the input data.…”

Section: Standard Methodsmentioning

confidence: 99%

Delayed Frontal Solution for Finite-Element based Resistance Extraction

Meijs

1995

32nd Design Automation Conference

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To save memory, layout-to-circuit extractors that use the Finite-Element Method for resistance extraction usually solve the corresponding set of equations with a frontal solution method. We show that this method is inefficient when used with a scanline ordering of the elements. As an improvement, we introduce the Delayed Frontal Solution algorithm, which allows us to replace the scanline ordering by the minimumdegree ordering. Thus, extraction times are reduced with more than one order of magnitude at a small cost of extra memory.

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Section: Standard Methodsmentioning

confidence: 99%

Delayed Frontal Solution for Finite-Element based Resistance Extraction

Meijs

1995

32nd Design Automation Conference

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“…For examples, MOR techniques that can handle delays or preserve passivity have been proposed [6][7][8][9]. Circuit reduction approaches based on Gaussian elimination have also been developed [10][11][12].…”

Section: Introductionmentioning

confidence: 99%

Deriving Meaningful Equivalent Circuits for Electrically Small Multi-Conductor Structures

Yeung¹

2016

PIER

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Abstract-A new circuit reduction algorithm for generating physically meaningful equivalent circuits for electrically small structures is proposed in this work. It makes use of the generalized Y-to-Δ transformation as well as features unique to partial element equivalent circuits (PEECs) to perform the reduction process. For a given partial element equivalent circuit, insignificant nodes are removed one by one in a prioritized order according to both user-specified cut-off frequency and threshold value. By having the freedom of choosing these parameters, this algorithm provides users an option to make a tradeoff between accuracy and simplicity of the final reduced circuit. Since the generalized Y-to-Δ transformation can keep all mutual couplings intact, the order-reduced circuit should correctly capture all physical essences of the structure being modeled. Two examples are presented in this paper to validate the proposed algorithm. The equivalent circuits obtained can indeed reflect all essential physical features, demonstrating that the algorithm is a useful tool for designing and analyzing electrically small multi-conductor structures.

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“…Such an interpretation of the FEM [1,2,11] initially produces a complex resistance network that models the resistive interconnections in detail. Subsequently, this network is reduced by a set of node eliminations.…”

Section: The Finite-element Methodsmentioning

confidence: 99%

“…Layout-to-circuit extractors usually use this circuit or graph formulation [2]. It is easier to implement efficiently and is compatible with the data structures for the device connectivity.…”

Section: The Finite-element Methodsmentioning

confidence: 99%

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Using articulation nodes to improve the efficiency of finite-element based resistance extraction

vanGenderen¹,

vanderMeiis²

33rd Design Automation Conference Proceedings, 1996

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In this paper, we describe how we have improved the efficiency of a finite-element method for interconnect resistance extraction by introducing articulation nodes in the finiteelement mesh. The articulation nodes are found by detecting equipotential regions and lines in the interconnects. Without generating inaccuracies, these articulation nodes split the finite-element mesh into small pieces that can be solved independently. The method has been implemented in the layoutto-circuit extractor Space. All interconnect resistances of a circuit containing 63,000 transistors are extracted on an HP 9000/735 workstation in approximately 70 minutes.

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Extracting simple but accurate RC models for VLSI interconnect

Cited by 21 publications

References 8 publications

Delayed Frontal Solution for Finite-Element based Resistance Extraction

Delayed Frontal Solution for Finite-Element based Resistance Extraction

Deriving Meaningful Equivalent Circuits for Electrically Small Multi-Conductor Structures

Using articulation nodes to improve the efficiency of finite-element based resistance extraction

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