Extracting functional modules from flattened gate-level netlist

Shi, Yong; Gwee, Bah-Hwee; Ren, Yi; Phone, Thet Khaing.; Ting, Chan Wai

doi:10.1109/iscit.2012.6380958

Cited by 14 publications

(2 citation statements)

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“…Functional Block Identification. One or multiple submodules of the netlist (after partitioning) can be matched to a library of known netlists or netlist structures to identify their high-level functionalities [16], [23]- [25]. Some approaches require a perfect match RR PF while other approaches enable fuzzy matching with only similar netlists but equal functionality RR PH .…”

Section: Functional Re -Netlist Abstractionmentioning

confidence: 99%

CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering

Ludwig¹,

Hepp²,

Brunner³

et al. 2022

Preprint

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Trust and security of microelectronic systems are a major driver for game-changing trends like autonomous driving or the internet of things. These trends are endangered by threats like soft- and hardware attacks or IP tampering -- wherein often hardware reverse engineering (RE) is involved for efficient attack planning. The constant publication of new RE-related scenarios and countermeasures renders a profound rating of these extremely difficult. Researchers and practitioners have no tools or framework which aid a common, consistent classification of these scenarios. In this work, this rating framework is introduced: the common reverse engineering scoring system (CRESS). The framework allows a general classification of published settings and renders them comparable. We introduce three metrics: exploitability, impact, and a timestamp. For these metrics, attributes are defined which allow a granular assessment of RE on the one hand, and attack requirements, consequences, and potential remediation strategies on the other. The system is demonstrated in detail via five case studies and common implications are discussed. We anticipate CRESS to evaluate possible vulnerabilities and to safeguard targets more proactively.

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Section: Functional Re -Netlist Abstractionmentioning

confidence: 99%

CRESS: Framework for Vulnerability Assessment of Attack Scenarios in Hardware Reverse Engineering

Ludwig¹,

Hepp²,

Brunner³

et al. 2022

Preprint

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“…In further work, Meade et al [25] developed a technique to separate control unit registers from datapath registers. In order to automatically reverse engineer functional submodules in a larger hardware design, diverse techniques have been developed based on Boolean function analysis [26], pattern mining of simulation traces and model checking [27], module boundary identification [28], [6], and word-level structure identification [29]. Since functional identification of subcircuits requires to find the correct matching between known subcircuits and the subcircuit under inspection, a reverse engineer has to find the correct input permutation.…”

Section: Gate-level Netlist Reverse Engineeringmentioning

confidence: 99%

Hardware reverse engineering: Overview and open challenges

Fyrbiak

Strauß

Kison

et al. 2017

2017 IEEE 2nd International Verification and Security Workshop (IVSW)

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Hardware reverse engineering is a universal tool for both legitimate and illegitimate purposes. On the one hand, it supports confirmation of IP infringement and detection of circuit malicious manipulations, on the other hand it provides adversaries with crucial information to plagiarize designs, infringe on IP, or implant hardware Trojans into a target circuit. Although reverse engineering is commonplace in practice, the quantification of its complexity is an unsolved problem to date since both technical and human factors have to be accounted for. A sophisticated understanding of this complexity is crucial in order to provide a reasonable threat estimation and to develop sound countermeasures, i.e. obfuscation transformations of the target circuit, to mitigate risks for the modern IC landscape.The contribution of our work is threefold: first, we systematically study the current research branches related to hardware reverse engineering ranging from decapsulation to gate-level netlist analysis. Based on our overview, we formulate several open research questions to scientifically quantify reverse engineering, including technical and human factors. Second, we survey research on problem solving and on the acquisition of expertise and discuss its potential to quantify human factors in reverse engineering. Third, we propose novel directions for future interdisciplinary research encompassing both technical and psychological perspectives that hold the promise to holistically capture the complexity of hardware reverse engineering.

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