Extension of Two-Signal Spurious-Free Dynamic Range of Wideband Digital Receivers Using Kaiser Window and Compensation Method

George, Kiran; Chen, C.-I.H.; Tsui, J.B.Y.

doi:10.1109/tmtt.2007.892818

Cited by 27 publications

(18 citation statements)

References 10 publications

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“…This disparity is the primary impediment in radar receiver design implementation, especially for single processor-based systems. Many practical digital receivers compensate the high sampling rate of ADCs to accommodate the speed at which the detection logic in the processor can +++ process the data [2] [3]. However, for real-time and more efficient operation, signal processors in digital radar receivers of the future will need to process data at a rate commensurate with the sampling speed of ADCs [4].…”

Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

“…Several techniques have been proposed to reduce the computational complexity of the FFT operations. The FFTs used in the Monobit receiver design [2] and ROC II [3] replace general multiplications in FFT with shift, addition or subtraction operations. The receiver employing a 2-bit ADC and a 256-point FFT implemented by a 4-point FFT kernel function can simultaneously detect two signals with an IDR of 5 dB in 1 GHz BW.…”

Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

“…The receiver employing a 2-bit ADC and a 256-point FFT implemented by a 4-point FFT kernel function can simultaneously detect two signals with an IDR of 5 dB in 1 GHz BW. An improvement of the Monobit receiver to extend the two-signal IDR to 24 dB was presented in [3]. This improved receiver design (ROC II) mainly consists of a 4-b ADC, a Kaiser window, a 256-point FFT implemented by a 12-point FFT kernel function, and a super-resolution block.…”

Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

“…The main blocks of each GPU are: 1) Window function (calculates the product of the data samples and the Kaiser window coefficient), 2) 4096-point 8-b FFT: (FFTW, a C subroutine library for computing the FFT), 3) Normalization (normalizes the 2048 FFT output amplitudes to a maximum value of 1), 4) Find "n" (find the row of highest amplitude (strongest) signal frequency spectrum in the compensation table, using the super-resolution algorithm [3]), 5) "Compensation LUT" and "Compensation" (extract the strongest signal frequency spectrum from the compensation table and subtract it from the original FFT outputs), and 6) Signal Frequency Detection (closely estimate the detected signal frequency, using the super-resolution algorithm).…”

Section: ) Windowing Super-resolution and Frequencymentioning

confidence: 99%

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Design and performance evaluation of a digital wideband receiver on a hybrid computing platform

George

Chen

2011

2011 IEEE International Instrumentation and Measurement Technology Conference

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Design and implementation of a modern radar receiver that is capable of rapidly searching a large frequency range with maximum sensitivity in real time presents a challenge. Such a receiver not only has stringent operational requirements like high instantaneous dynamic range (IDR), multiple signal detection capability, wider bandwidth and also high frequency resolution. Currently, operating speeds of digital processors are not on par with state-of-the-art ADCs. To overcome this impediment, researchers are exploring methods of offloading the computational intensive tasks to specialized hardware accelerators. A 3 giga-sample-per-second (GSPS) wideband digital receiver system implemented on a unique hybrid computing platform, which is composed of two Tesla C2050 GPUs and a Xilinx Virtex-5 FPGA, is presented. Drastically improving its performance over its predecessors, the proposed receiver system detects five simultaneous signals in 1.25 GHz bandwidth (125 -1375 MHz) with a maximum IDR of 42.5 dB and a frequency resolution of 0.5 MHz. The proposed receiver architecture performs a high-resolution spectral estimation and employs a hardware efficient platform for detecting multiple signals before the next set of buffered data arrives for processing.

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Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

Section: Digital Receiver On Single Processor Platformmentioning

confidence: 99%

Section: ) Windowing Super-resolution and Frequencymentioning

confidence: 99%

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Design and performance evaluation of a digital wideband receiver on a hybrid computing platform

George

Chen

2011

2011 IEEE International Instrumentation and Measurement Technology Conference

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“…The dynamic kernel function algorithm is an extension of the fixed-point kernel function used in [6], where the unit circle of the phase function W N is expanded by higher powers of two. The precision of the dynamic kernel function is determined by the number of bits intended to represent the twiddle factors.…”

Section: Introductionmentioning

confidence: 99%

Bit-precision and performance analysis of dynamic kernel function fast fourier transform

Lee

Chen

2010

2010 IEEE Instrumentation &Amp; Measurement Technology Conference Proceedings

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The proposed dynamic kernel function uses an efficient fixed-point numerical representation of the twiddle factor (i.e., complex roots of unity) and replaces the cumbersome multipliers in FFT with simple shift-and-add operations to enhance the data throughput rate for high-speed wideband signal detection. Numerical representation in hardware plays a role in determining the dynamic range and bit precision of FFT processors. The proposed variable truncation scheme dynamically scales the computation data and maximizes the use of fixed-input and inter-stage wordlength in a fixed-point FFT. The dynamic data scaling algorithm enhances the dynamic range of fixed-point fixed-precision FFT designs and emulates the precision benefits of floating-point representation without complicated design additions. The development of dynamic kernel function FFT performance models using different variations of inter-stage bit precision shows a relative trade-off between precision bits to FFT SFDR.Keywords -Fast Fourier transform (FFT), spurious-free dynamic range (SFDR), and dynamic kernel function FFT.

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High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding

Feiran

Chen

2020

Integration

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Extension of Two-Signal Spurious-Free Dynamic Range of Wideband Digital Receivers Using Kaiser Window and Compensation Method

Cited by 27 publications

References 10 publications

Design and performance evaluation of a digital wideband receiver on a hybrid computing platform

Design and performance evaluation of a digital wideband receiver on a hybrid computing platform

Bit-precision and performance analysis of dynamic kernel function fast fourier transform

High two-signal dynamic range and accurate frequency measurement for close frequency separation wideband digital receiver using adaptive gain control and adaptive thresholding

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