Extensible Recognition of Algorithmic Patterns in DSP Programs for Automatic Parallelization

Sarvestani, Amin Shafiee; Hansson, Erik; Keßler, Christoph

doi:10.1007/s10766-012-0229-2

Cited by 7 publications

(3 citation statements)

References 14 publications

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“…It then uses a data-dependence analysis to prove that all loop iterations refer to different elements of the reduced array. Sarvestani et al introduced an idiom-detection tool for kernel recognition in DSP applications based on the Cetus compiler [30,41]. Each detected kernel is replaced with a highly optimized parallel version.…”

Section: Related Workmentioning

confidence: 99%

Declarative Loop Tactics for Domain-specific Optimization

Chelini

Zinenko

Grosser

et al. 2019

ACM Trans. Archit. Code Optim.

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Increasingly complex hardware makes the design of effective compilers difficult. To reduce this problem, we introduce Declarative Loop Tactics, which is a novel framework of composable program transformations based on an internal tree-like program representation of a polyhedral compiler. The framework is based on a declarative C++ API built around easy-to-program matchers and builders, which provide the foundation to develop loop optimization strategies. Using our matchers and builders, we express computational patterns and core building blocks, such as loop tiling, fusion, and data-layout transformations, and compose them into algorithm-specific optimizations. Declarative Loop Tactics (Loop Tactics for short) can be applied to many domains. For two of them, stencils and linear algebra, we show how developers can express sophisticated domain-specific optimizations as a set of composable transformations or calls to optimized libraries. By allowing developers to add highly customized optimizations for a given computational pattern, we expect our approach to reduce the need for DSLs and to extend the range of optimizations that can be performed by a current general-purpose compiler. CCS Concepts: • Software and its engineering → Compilers;

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Section: Related Workmentioning

confidence: 99%

Declarative Loop Tactics for Domain-specific Optimization

Chelini

Zinenko

Grosser

et al. 2019

ACM Trans. Archit. Code Optim.

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“…FFT. This is a quite difficult problem to automate, however some progress has been made by another division involved in the same project [4].…”

Section: Goals and Scopementioning

confidence: 99%

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Sohl

2015

Linköping Studies in Science and Technology. Dissertations

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Modern signal processing systems require more and more processing capacity as times goes on. Previously, large increases in speed and power efficiency have come from process technology improvements. However, lately the gain from process improvements have been greatly reduced.Currently, the way forward for high-performance systems is to use specialized hardware and/or parallel designs.Application Specific Integrated Circuits (ASICs) have long been used to accelerate the processing of tasks that are too computationally heavy for more general processors. The problem with ASICs is that they are costly to develop and verify, and the product life time can be limited with newer standards. Since they are very specific the applicable domain is very narrow.More general processors are more flexible and can easily adapt to perform the functions of ASIC based designs. However, the generality comes with a performance cost that renders general designs unusable for some tasks. The question then becomes, how general can a processor be while still being power efficient and fast enough for some particular domain?Application Specific Instruction set Processors (ASIPs) are processors that target a specific application domain, and can offer enough performance with power efficiency and silicon cost that is comparable to ASICs.The flexibility allows for the same hardware design to be used over several system designs, and also for multiple functions in the same system, if some functions are not used simultaneously.iii iv One problem with ASIPs is that they are more difficult to program than a general purpose processor, given that we want efficient software.Utilizing all of the features that give an ASIP its performance advantage can be difficult at times, and new tools and methods for programming them are needed.This thesis will present ePUMA (embedded Parallel DSP platform with Unique Memory Access), an ASIP architecture that targets algorithms with predictable data access. These kinds of algorithms are very common in e.g. baseband processing or multimedia applications. The primary focus will be on the specific features of ePUMA that are utilized to achieve high performance, and how it is possible to automatically utilize them using tools. The most significant features include data permutation for conflict-free data access, and utilization of address generation features for overhead free code execution. This sometimes requires specific information; for example the exact sequences of addresses in memory that are accessed, or that some operations may be performed in parallel. This is not always available when writing code using the traditional way with traditional languages, e.g. C, as extracting this information is still a very active research topic. In the near future at least, the way that software is written needs to change to exploit all hardware features, but in many cases in a positive way. Often the problem with current methods is that code is overly specific, and that a more general abstractions are actually easier to ge...

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“…It would also be interesting to test this on heterogeneous systems such as CPU-GPU based ones, especially if we apply our technique for loop unrolling. Another interesting problem would be to derive parameterized models of algorithms using a pattern matching framework such as PRT [85] and combine it with machine learning. Each pattern could then be annotated with a predictor for the pattern implementations' best performance for specific parameter values and for a given type of hardware.…”

Section: Future Workmentioning

confidence: 99%

Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture

Hansson¹

2014

Self Cite

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In this thesis we describe techniques for code generation and global optimization for a PRAM-NUMA multicore architecture. We specifically focus on the REPLICA architecture which is a family massively multithreaded very long instruction word (VLIW) chip multiprocessors with chained functional units that has a reconfigurable emulated shared on-chip memory. The on-ship memory system supports two execution modes, PRAM and NUMA, which can be switched between at run-time.PRAM mode is considered the standard execution mode and targets mainly applications with very high thread level parallelism (TLP). In contrast, NUMA mode is optimized for sequential legacy applications and applications with low amount of TLP. Different versions of the REPLICA architecture have different number of cores, hardware threads and functional units. In order to utilize the REPLICA architecture efficiently we have made several contributionsto the development of a compiler for REPLICA target code generation. It supports both code generation for PRAM mode and NUMA mode and can generate code for different versions of the processor pipeline (i.e. for different numbers of functional units). It includes optimization phases to increase the utilization of the available functional units. We have also contributed to quantitative the evaluation of PRAM and NUMA mode. The results show that PRAM mode often suits programs with irregular memory access patterns and control flow best while NUMA mode suites regular programs better. However, for a particular program it is not always obvious which mode, PRAM or NUMA, will show best performance. To tackle this we contributed a case study for generic stencil computations, using machine learning derived cost models in order to automatically select at runtime which mode to execute in. We extended this to also include a sequence of kernels

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Extensible Recognition of Algorithmic Patterns in DSP Programs for Automatic Parallelization

Cited by 7 publications

References 14 publications

Declarative Loop Tactics for Domain-specific Optimization

Declarative Loop Tactics for Domain-specific Optimization

Efficient Compilation for Application Specific Instruction set DSP Processors with Multi-bank Memories

Code Generation and Global Optimization Techniques for a Reconfigurable PRAM-NUMA Multicore Architecture

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