Extending the roadmap beyond 3nm through system scaling boosters: A case study on Buried Power Rail and Backside Power Delivery

Ryckaert, Julien; Gupta, Anshul; Jourdain, Anne; Chava, Bharani; Plas, G. Van der; Verkest, D.; Beyne, Eric

doi:10.1109/edtm.2019.8731234

Cited by 36 publications

(12 citation statements)

References 3 publications

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“…Ru and W are the two promising materials for BPR [ 8 , 9 , 10 ] for their high thermal budgets, relatively low resistance, and superior anti-electromigration properties. It has been reported that high-aspect-ratio (AR) Ru BPR demonstrates excellent resistivity reduction [ 8 ].…”

Section: Resultsmentioning

confidence: 99%

“…This effect increases the resistance–capacitance (RC) delay, current-resistance (IR) drop, and power consumption at M0 and M1, and thus deteriorates BEOL’s performance [ 3 ]. Many efforts have been devoted to improving the BEOL’s performance, from metallization to the structures’ perspective, respectively [ 3 , 4 , 5 , 6 , 7 , 8 , 9 , 10 ].…”

Section: Introductionmentioning

confidence: 99%

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Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Zhao

et al. 2022

Nanomaterials

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The resistivity of Cu interconnects increases rapidly with continuously scaling down due to scatterings, causing a major challenge for future nodes in M0 and M1 layers. Here, A Boltzmann-transport-equation-based Monte Carlo simulator, including all the major scattering mechanisms of interconnects, is developed for the evaluation of electron transport behaviors. Good agreements between our simulation and the experimental results are achieved for Cu, Ru, Co, and W, from bulk down to 10 nm interconnects. The line resistance values of the four materials with the inclusion of liner and barrier thicknesses are calculated in the same footprint for a fair comparison. The impact of high aspect ratio on resistivity is analyzed for promising buried power rail materials, such as Ru and W. Our results show that grain boundary scattering plays the most important role in nano-scale interconnects, followed by surface roughness and plasma excimer scattering. Surface roughness scattering is the origin of the resistivity decrease for high-aspect-ratio conductive rails. In addition, the grain sizes for the technical nodes of different materials are extracted and the impact of grain size on resistivity is analyzed.

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Section: Resultsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Mechanisms of Scaling Effect for Emerging Nanoscale Interconnect Materials

Zhao

et al. 2022

Nanomaterials

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“…To explore the scaling impact of many-tier VFETs on cell-level and block-level area, we select and generate 30 representative SDCs [33], [34] as specified in Table III for many-tier 7T VFET architecture with the number of tiers ranging 1-4 tiers by using ASAP7 [35] SDC netlists. We also generate 4.5T GAA Nanosheet FET (GAAFET) SDCs with buried power rails by scaling 4.5T FinFET SDCs [36], based on the effective width ratio [37] between FinFET and Nanosheet structures with the concurrent P&R framework [20] for the comparison with VFETs.…”

Section: Resultsmentioning

confidence: 99%

Many-Tier Vertical Gate-All-Around Nanowire FET Standard Cell Synthesis for Advanced Technology Nodes

Lee

Kang

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Many-tier vertical gate-all-around nanowire FET (VFET) synthesis strongly demands a holistic approach of modeling/formulating/optimizing transistor placement and in-cell routing to obtain the maximum-achievable PPAC (power, performance, area, and cost) benefits. In this paper, we propose a novel SMT (Satisfiability Modulo Theories)-based many-tier VFET standard cell (SDC) synthesis framework that simultaneously solves place-and-route (P&R). We devise an extended relative positioning constraint and a dummy gate control scheme to capture the unique VFET cell architecture. Moreover, we present efficient objectives to improve pin-accessibility and reduce the use of vertical routing, which has high resistance. Compared to the conventional sequential P&R approach, our concurrent P&R achieves a 15.2% smaller cell area on average for 2tier VFET. Throughout the extensive exploration for many-tier VFET configurations up to 4-tier, we show that the 4-tier VFET respectively achieves 50.1% and 27.9% of average area reduction on chip-level and block-level, over 4.5T GAAFET.

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“…For the fair comparison in terms of our metrics, we adopt the same in-cell horizontal routing tracks (i.e., 4 tracks) and push the SDC power rail to BPR layer for Conv. SDC structure [ 17] . Figure 8 shows the netlist and the generated CFET cell layout of an XOR2xl SDC.…”

Section: Cfet Vs Conv Cell Layoutmentioning

confidence: 99%