Extending OpenMP For NUMA Machines

Bircsak, John; Craig, Peter; Crowell, RaeLyn; Cvetanovic, Zarka; Harris, Jonathan; Nelson, Chris; Offner, Carl D.

doi:10.1109/sc.2000.10019

Cited by 47 publications

(22 citation statements)

References 1 publication

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“…As has previously been demonstrated for individual applications [8][9][10][11], this section provides an example which confirms that performance improvements over state of the art schemes can be achieved by adding application awareness to the page placement (PP) process. We use the NAS-PB Fourier Transformation (ft) benchmark as a casestudy.…”

Section: Motivating Examplesupporting

confidence: 71%

NUMA Optimizations for Algorithmic Skeletons

Metzger

Cole

Fensch

2018

Euro-Par 2018: Parallel Processing

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To address NUMA performance anomalies, programmers often resort to application specific optimizations that are not transferable to other programs, or to generic optimizations that do not perform well in all cases. Skeleton based programming models allow NUMA optimizations to be abstracted on a pattern-by-pattern basis, freeing programmers from this complexity. As a case study, we investigate computations that can be implemented with stencil skeletons. We present an analysis of the behavior of a range of simple and complex stencil programs from the NAS and Rodinia benchmark suites, under state-ofthe-art NUMA aware page placement (PP) schemes. We show that even though an application (or skeleton) may have implemented the correct, intuitive scheduling of data and work to threads, the resulting performance can be disrupted by an inappropriate PP scheme. In contrast, we show that a NUMA PP-aware stencil implementation scheme can achieve speed ups of up to 12x over a similar scheme which uses the Linux default PP, and that this works across a set of complex stencil applications. Furthermore, we show that a supposed PP performance optimization in the Linux kernel never improves and in some cases degrades stencil performance by up to 0.27x and should therefore be deactivated by stencil skeleton implementations. Finally, we show that further speed ups of up to 1.1x can be achieved by addressing a work imbalance issue caused by poor conventional understanding of NUMA PP.

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Section: Motivating Examplesupporting

confidence: 71%

NUMA Optimizations for Algorithmic Skeletons

Metzger

Cole

Fensch

2018

Euro-Par 2018: Parallel Processing

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“…NUMA is commonly used in modern multi-processor systems to avoid the bottleneck of shared memory accesses [32]. It provides asymmetric memory bandwidth and latency characteristics [33].…”

Section: Related Workmentioning

confidence: 99%

“…For example, an NUMA API for Linux was proposed in [36] which allows programmers to make memory allocations from a specific node or memory module, in addition to binding threads to specific CPUs. Different algorithms have been proposed to spread application data across different memories of an NUMA platform, such as round-robin, first touch affinity and next-touch affinity [32,37]. An extension to Linux kernel to add support for the affinity-on-next-touch algorithm is reported in [38].…”

Section: Related Workmentioning

confidence: 99%

“…In this work, we exploit the availability of dual load-store Units to processors of a vision-processing system and its NUMA architecture, where memory is divided into multiple slices, each one having an affinity to one of the processors. Unlike the traditional memory affinity approach focusing on the reduction of latency by placing data closer to the computing processor [32,33,37,39], the purpose of our affinity analysis is to reduce the memory bound stalls by taking into account memory organization and hence efficiently scheduling memory accesses.…”

Section: Related Workmentioning

confidence: 99%

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Exploiting architectural features of a computer vision platform towards reducing memory stalls

Mustafa

O’Riordan

Rogers

et al. 2018

J Real-Time Image Proc

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Computer vision applications are becoming more and more popular in embedded systems such as drones, robots, tablets, and mobile devices. These applications are both compute and memory intensive, with memory bound stalls (MBS) making a significant part of their execution time. For maximum reduction in memory stalls, compilers need to consider architectural details of a platform and utilize its hardware components efficiently. In this paper, we propose a compiler optimization for a vision-processing system through classification of memory references to reduce MBS. As the proposed optimization is based on the architectural features of a specific platform, i.e., Myriad 2, it can only be applied to other platforms having similar architectural features. The optimization consists of two steps: affinity analysis and affinity-aware instruction scheduling. We suggest two different approaches for affinity analysis, i.e., source code annotation and automated analysis. We use LLVM compiler infrastructure for implementation of the proposed optimization. Application of annotation-based approach on a memory-intensive program shows a reduction in stall cycles by 67.44%, leading to 25.61% improvement in execution time. We use 11 different image-processing benchmarks for evaluation of automated analysis approach. Experimental results show that classification of memory references reduces stall cycles, on average, by 69.83%. As all benchmarks are both compute and memory intensive, we achieve improvement in execution time by up to 30%, with a modest average of 5.79%.

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“…In particular, Lepers et al improved memory page migration algorithms to consider memory asymmetry [18]. There is also research that investigated data placement on NUMA machines [28,52,53,54]. These techniques aim to reduce memory latency rather than reducing bandwidth usage.…”

Section: Related Workmentioning

confidence: 99%

Predicting the memory bandwidth and optimal core allocations for multi-threaded applications on large-scale NUMA machines

Wang

Davidson

Soffa

2016

2016 IEEE International Symposium on High Performance Computer Architecture (HPCA)

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Modern NUMA platforms offer large numbers of cores to boost performance through parallelism and multi-threading. However, because performance scalability is limited by available memory bandwidth, the strategy of allocating all cores can result in degraded performance. Consequently, accurately predicting optimal (best performing) core allocations, and executing applications with these allocations are crucial for achieving the best performance. Previous research focused on the prediction of optimal numbers of cores. However, in this paper, we show that, because of the asymmetric NUMA memory configuration and the asymmetric application memory behavior, optimal core allocations are not merely optimal numbers of cores. Additionally, previous studies do not adequately consider NUMA memory resources, which further limits their ability to accurately predict optimal core allocations. In this paper, we present a model, NuCore, which predicts both memory bandwidth usage and optimal core allocations. NuCore considers various memory resources and NUMA asymmetry, and employs Integer Programming to achieve high accuracy and low overhead. Experimental results from real NUMA machines show that the core allocations predicted by NuCore provide 1.27x average speedup over using all cores with only 75.6% cores allocated. Nu-Core also provides 1.18x and 1.21x average speedups over two state-of-the-art techniques. Our results also show that NuCore faithfully models NUMA memory systems and predicts memory bandwidth usages with only 10% average error.

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Extending OpenMP For NUMA Machines

Abstract: Abstract

Cited by 47 publications

References 1 publication

NUMA Optimizations for Algorithmic Skeletons

NUMA Optimizations for Algorithmic Skeletons

Exploiting architectural features of a computer vision platform towards reducing memory stalls

Predicting the memory bandwidth and optimal core allocations for multi-threaded applications on large-scale NUMA machines

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