Extending Booth algorithm to multiplications of three numbers on FPGAs

Asher, Yosi Ben; Stein, Esti

doi:10.1109/fpt.2008.4762411

Cited by 3 publications

(6 citation statements)

References 2 publications

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“…By this we assume that all the TAI operations have the two properties of (a) fast circuits and (b) partition to pipeline stages that are needed for modern CPUs. (see Ben Asher and Stein [2] for an extension of Booth technique to handle MUL3).…”

Section: Using Three Argument Instructionsmentioning

confidence: 97%

“…For example, HR can transform a chain of additions to a binary tree of additions thus reducing its critical path to log of the original length. 2 VLIW scheduling is the problem of determining a minimal sequence of VLIW instructions (wide instructions that executes several operations in parallel) that, when executed, evaluates a given AC. Obviously the critical path of the AC bounds from bellow the number of VLIW instructions needed to evaluate it.…”

Section: Introductionmentioning

confidence: 99%

“…The AC which is addressed in this work is equivalent to a basic block, i.e., we convert basic blocks to ACs 2. In general HR is NP-complete as it can be reduced to 3-SAT based on the fact that it is easy to code a boolean formula by an AC and ask if it can be reduced to 0 (non satisfiable assignment exists).…”

mentioning

confidence: 99%

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Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Abboud

Ben-Asher

Shajrawi

et al. 2012

Int J Parallel Prog

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In here we consider a technique to automatically extract three-argument instructions from sequential arithmetic code. The instructions include: multiply and add, three argument additions and three argument multiplications (MUL3). The proposed solution combines a height reduction technique that generates three-argument instructions and a VLIW scheduling that can benefit from these instructions. The proposed height reduction technique is based on a known theoretical algorithm (MRK) that in some cases can evaluate an algebraic circuit faster than its depth. We modified the MRK algorithm to generate less instructions and emit VLIW instructions. The modified MRK algorithm was implemented in the LLVM compiler and the potential usefulness was measured. Our results show that for arithmetic benchmarks the proposed technique can improve the VLIW scheduling while emitting three-argument instructions. The contribution of this work includes: the modified MRK algorithm as a new technique for height reduction optimizations and the study of the potential usefulness of three-argument instructions. Though our results are for a non existing hardware they show the usefulness of adding such instructions to VLIW CPUs. Note that a previous research showed that MUL3 can be executed as fast as MUL2.

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Section: Using Three Argument Instructionsmentioning

confidence: 97%

Section: Introductionmentioning

confidence: 99%

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Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Abboud

Ben-Asher

Shajrawi

et al. 2012

Int J Parallel Prog

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“…Thus there is a need to find a practical algorithm for multiplying three integers. The proposed RM algorithm uses a general scheme for three numbers multiplication (EBooth) proposed in [1]. This is an extension of the well known Booth algorithm for 2-mull.…”

Section: Introductionmentioning

confidence: 99%

“…For example, multiplying y by 01111100 will produce two addends (adding y shifted to the MSB, and subtracting y shifted left twice) rather than producing five addends, adding y shifted left twice to sixth times each, consecutively. In this work we use the EBooth scheme [1] as a basis to develop a practical algorithm for multiplying three integers on the RM. This is due to the use of simple operations rather then using the Chinese Reminder theorem (used in [8]) or Radar Transform in a multidimensional space (used in [3]), which implies complexity of O(1) yet hidden large constants, as mentioned above.…”

Section: Introductionmentioning

confidence: 99%

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh

Stein

Asher

2014

2014 IEEE International Parallel &Amp; Distributed Processing Symposium Workshops

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This paper presents a three-integers multiplication algorithm R = A * X * Y for Reconfigurable Mesh (RM). It is based on a three-integer multiplication algorithm for faster FPGA implementations. We show that multiplying three integers of n bits can be performed on a 3D RM of size (3n +log n + 1)× (2 √ n + 1+3)× √ n + 1 using 44 + 18 · log log MNO steps, where MNO is a bound which is related to the number of sequences of '1's in the multiplied numbers. The value of MNO is bounded by n but experimentally we show that on the average it is √ n. Two algorithms for solving multiplication on a RM exists and their techniques are asymptotically better time wise, O(1) and O(log * n), but they suffer from large hidden constants and slow data insertion time ( O( √ n)) respectively. The proposed algorithm is relatively simple and faster on the average (via sampling input values) then the previous two algorithms thus contributes in making the RM a practical and feasible model. Our experiments show a significant improvement in the expected number of elementary operations for the proposed algorithm.

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Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems

Bureneva

Mironov

2023

Electronics

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Traditionally, the usual multipliers are used to multiply signals by a constant, but multiplication by a constant can be considered as a special operation requiring the development of specialized multipliers. Different methods are being developed to accelerate multiplications. A large list of methods implement multiplication on a group of bits. The most known one is Booth’s algorithm, which implements two-digit multiplication. We propose a modification of the algorithm for the multiplication by three digits at the same time. This solution reduces the number of partial products and accelerates the operation of the multiplier. The paper presents the results of a comparative analysis of the characteristics of Booth’s algorithm and the proposed algorithm. Additionally, a comparison with built-in FPGA multipliers is illustrated.

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Extending Booth algorithm to multiplications of three numbers on FPGAs

Cited by 3 publications

References 2 publications

Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Combining Height Reduction and Scheduling for VLIW Machines Enhanced with Three-Argument Arithmetic Operations

Adaptive Booth Algorithm for Three-Integers Multiplication for Reconfigurable Mesh

Fast FPGA-Based Multipliers by Constant for Digital Signal Processing Systems

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