Extended lattice-based memory allocation

Abstract

This work extends lattice-based memory allocation, an earlier work on memory (array) reuse analysis. The main motivation is to handle in a better way the more general forms of specifications we see today, e.g., with loop tiling, pipelining, and other forms of parallelism available in explicitly parallel languages. Our extension has two complementary aspects. We show how to handle more general specifications where conflicting constraints (those that describe the array indices that cannot share the same location) are specified as a (non-convex) union of polyhedra. Unlike convex specifications, this also requires to be able to choose suitable directions (or basis) of array reuse. For that, we extend two dual approaches, previously proposed for a fixed basis, into optimization schemes to select suitable basis. Our final approach relies on a combination of the two, also revealing their links with, on one hand, the construction of multi-dimensional schedules for parallelism and tiling (but with a fundamental difference that we identify) and, on the other hand, the construction of universal reuse vectors (UOV), which was only used so far in a specific context, for schedule-independent mapping.

DeLICM: scalar dependence removal at zero memory cost

“…There is the possibility to contract array space after scheduling [6,7,11,19,25,34]. However, the re-scheduled program may inherently require more memory than the source program, especially if the scheduler is unaware that its decisions may increase the memory footprint.…”

“…A conflict set as presented in [7,11] can be useful to determine whether a scalar is conflicting with an array (Listing 6 line 13). For the purpose of DeLICM we additionally need to analyze the stored content.…”

PCOT: Cache Oblivious Tiling of Polyhedral Programs

“…[19] took a fresh and elegant approach to the problem, and formulated the conditions for legal memory allocations by defining the conflict set. This led to techniques for choosing provably optimal memory allocations, initially for non-parameterized iteration spaces, and recently in the context of FPGA acelerators, for parametrically tiled spaces [16,17]. Vasilache et al [64] developed a tool to combine the scheduling and limiting memory expansion using an ILP formulation, implemented in the R-Stream compiler.…”