Extended Double Carrier PWM Strategy Dedicated to RMS Current Reduction in DC Link Capacitors of Three-Phase Inverters

Nguyen, Truong X.; Patin, Nicolas; Friedrich, Guy

doi:10.1109/tpel.2013.2251005

“…In [7][8][9], the dc-link current spectra are described by a double Fourier series. A new PWM strategy, called extended double carrier PWM, for a two-level three-phase inverters has been proposed in [10] aiming at reducing the RMS current flowing through the dc-link capacitors. The RMS values and frequency spectra of the capacitor current in three-phase EV drive systems are analyzed in [11] with respect to three modulation strategies and various operating conditions.…”

Section: Introductionmentioning

confidence: 99%

Evaluation of DC-Link Voltage Switching Ripple in Multiphase PWM Voltage Source Inverters

Vujacic

¹

,

Dordevic

²

,

Grandi

³

2020

IEEE Trans. Power Electron.

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“…For example, research has been published detailing analyses of capacitor current and loss in a three‐phase inverter, and methods for reducing capacitor current have been proposed . However, these studies assume an ideal DC‐link capacitor configuration and, as such, it can be said that there have not been any detailed reports made for a practical circuit configuration in which a plurality of capacitor cells are connected in parallel.…”

Section: Introductionmentioning

confidence: 99%

Capacitor current imbalance and its suppression method between phase legs for three‐phase inverter

Hirao

¹

,

Wãda

²

,

Shimizu

³

2019

Electrical Engineering Japan

0

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This paper proposes a method to suppress the capacitor current imbalance between the phase legs of a three-phase inverter circuit. This circuit consists of half-bridge modules and DC-link capacitors closely connected to each module. It can be designed for low stray inductance between power semiconductor devices and DC-link capacitors in each module. However, in the conventional structure, the stray inductance between the phase legs may lead to an imbalance in the capacitor current due to the DC-side resonance phenomenon under a higher switching frequency condition by using a SiC MOSFET. This paper presents the analyses of the equivalent circuit considering the circuit configuration, which suggests that capacitor current imbalance occurs depending on the stray inductance between phase legs. To suppress the capacitor current imbalance, a delta-type bus bar connecting phase legs is proposed. The experiment results at 300 V and 4.6 A demonstrate the suppression effectiveness of the proposed method. K E Y W O R D Scurrent imbalance, DC-link capacitor, resonance, stray inductance, switching frequency Electr Eng Jpn. 2019;206:45-54.

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“…[1][2][3][4][5] For example, research has been published detailing analyses of capacitor current and loss in a three-phase inverter, 6,7 and methods for reducing capacitor current have been proposed. [8][9][10][11] However, these studies assume an ideal DClink capacitor configuration and, as such, it can be said that there have not been any detailed reports made for a practical circuit configuration in which a plurality of capacitor cells are connected in parallel. Figure 1 illustrates a practical application of an inverter consisting of a plurality of parallel-connected capacitor cells.…”

Section: Introductionmentioning

confidence: 99%

Capacitor Current Imbalance and Its Suppression Method Between Phase Legs for Three-phase Inverter

Hirao

¹

,

Wãda

²

,

Shimizu

³

2018

IEEJ Trans. IA

1

0

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This paper proposes a method to suppress the capacitor current imbalance between the phase legs of a three-phase inverter circuit. This circuit consists of half-bridge modules and DC-link capacitors closely connected to each module. It can be designed for low stray inductance between power semiconductor devices and DC-link capacitors in each module. However, in the conventional structure, the stray inductance between the phase legs may lead to an imbalance in the capacitor current due to the DC-side resonance phenomenon under a higher switching frequency condition by using a SiC MOSFET. This paper presents the analyses of the equivalent circuit considering the circuit configuration, which suggests that capacitor current imbalance occurs depending on the stray inductance between phase legs. To suppress the capacitor current imbalance, a delta-type bus bar connecting phase legs is proposed. The experiment results at 300 V and 4.6 A demonstrate the suppression effectiveness of the proposed method. K E Y W O R D Scurrent imbalance, DC-link capacitor, resonance, stray inductance, switching frequency Electr Eng Jpn. 2019;206:45-54.

show abstract

Extended Double Carrier PWM Strategy Dedicated to RMS Current Reduction in DC Link Capacitors of Three-Phase Inverters

Cited by 52 publications

References 16 publications

Evaluation of DC-Link Voltage Switching Ripple in Multiphase PWM Voltage Source Inverters

Evaluation of DC-Link Voltage Switching Ripple in Multiphase PWM Voltage Source Inverters

Capacitor current imbalance and its suppression method between phase legs for three‐phase inverter

Capacitor Current Imbalance and Its Suppression Method Between Phase Legs for Three-phase Inverter

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