Extended boost active switch‐controlled switched inductor‐based Z‐source inverter

Abstract

The presented topology in this paper represents a boosting topology known as extended boost active switch-controlled switched inductor Z-source inverter (EBASCSI-ZSI). The presented topology has the ability to provide high boost output voltage with lower shoot-through duty cycle. Three existing topologies in the field of Z-source inverter, namely, qZSI, DA-qZSI, and CA-qZSI, have been compared with the presented topology. It has been found that the boosting factor of the presented topology is higher compared to the three topologies. The presented topology has used the same number of inductors and a less capacitor compared to CA-qZSI topology, the same number of inductors and capacitors as compared to DA-qZSI topology, a more capacitor, and an inductor compared to qZSI topology. The voltage stress across the capacitors of the presented topology is approximately the same compared to CA-qZSI topology at higher shoot-through state, and the voltage stress is more compared to DA-qZSI and qZSI topologies at the same shoot-through state. The current stress across the inductors of the presented topology is similar across some inductors of the DA-qZSI and CA-qZSI topologies while in some other inductors, it is lower than that of CA-qZSI topology. The presented topology has been designed with a common ground between the source and inverter bridge while drawing continuous current from the source. The simulation model and its hardware prototype have been developed in the laboratory. The theoretical formulae obtained from the proposed model are matching with outcome of the simulation and hardware model.

Multi‐port single‐phase inverter considering battery‐alone mode for stand‐alone applications

“…Figure 17A illustrates CSF curves of the diodes for the proposed converter compared to previous studies. 17,[22][23][24] The results prove the excellence of both the proposed converter and the converter in Yousefi Moghadam et al 24 for 0 ≤ d ST ≤ 0.12. According to the experimental results, the working range of the d ST for the proposed converter is under 0.1.…”

“…In addition, the stress of D 4 and D 5 has lower values for different voltage gains in comparison to all the diodes except D 2 in Zhu et al 22 and D 4 and D 6 in Das and Panda. 23 Although the curve of voltage stress on D 3 for the proposed converter is located in the middle of the other curves, each of the compared converters includes at least one diode with higher voltage stress.…”

“…The next level can be defined for the capacitors that are located in the middle section of the converters such as C 4 in the proposed converter. The converters in previous studies 17,23,24 contain the capacitors with similar positions which are named C 1 in Abbasi et al, 17 C 2 in Das and Panda, 23 and C 5 in Yousefi Moghadam et al 24 Based on the curves in Figure 12, C 4 in the proposed converter has the lowest voltage stress in all voltage gains. Finally, in the third level, the capacitors in the output side of the proposed converter ( C 4 and C 5 ) have moderate condition compared to the same ones in other converters.…”

“…Equations ( 21) and ( 22) are used to eliminate V C1 and obtain V C2 related to duty cycles, voltage of input source (V 1 ) and V b such as shown in (23).…”

“…The voltage stress of the capacitors is obtained by analyzing the circuit in Figure 2 for the single input mode. Figure 12 is drawn based on the equations and analysis in previous studies 17,[22][23][24] that present single port DC-AC inverters. By referring to the converters configurations, we understand that they include capacitors with three levels of voltage stress depending on the location of the capacitors in the circuit.…”