Exploring the potential of heterogeneous von neumann/dataflow execution models

NowatzkiTony,; GangadharVinay,; SankaralingamKarthikeyan,

doi:10.1145/2872887.2750380

Cited by 13 publications

(8 citation statements)

References 34 publications

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“…There is a rich body of work regarding the potentials of dataflow based engines in general, and particularity coarse grained reconfigurable arrays. DySER [3], SEED [18], and MAD [19] extend von-Neumann based processors with dataflow engines that efficiently execute code blocks in a dataflow manner. Garp [20] adds a CGRA component to a simple core in order to accelerate loops.…”

Section: Related Work Dataflow Architectures and Cgrasmentioning

confidence: 99%

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays

Voitsechov

Port

Etsion

2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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Traditional von Neumann GPGPUs only allow threads to communicate through memory on a group-to-group basis. In this model, a group of producer threads writes intermediate values to memory, which are read by a group of consumer threads after a barrier synchronization. To alleviate the memory bandwidth imposed by this method of communication, GPGPUs provide a small scratchpad memory that prevents intermediate values from overloading DRAM bandwidth. In this paper we introduce direct inter-thread communications for massively multithreaded CGRAs, where intermediate values are communicated directly through the compute fabric on a point-to-point basis. This method avoids the need to write values to memory, eliminates the need for a dedicated scratchpad, and avoids workgroup-global barriers. The paper introduces the programming model (CUDA) and execution model extensions, as well as the hardware primitives that facilitate the communication. Our simulations of Rodinia benchmarks running on the new system show that direct inter-thread communication provides an average speedup of 4.5× (13.5× max) and reduces system power by an average of 7× (33× max), when compared to an equivalent Nvidia GPGPU.

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Section: Related Work Dataflow Architectures and Cgrasmentioning

confidence: 99%

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays

Voitsechov

Port

Etsion

2018

2018 51st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…WaveScalar (Swanson et al 2003) and SEED (Nowatzki et al 2015) are out-of-order dataflow architectures. The former focuses on solving the problem of long wire delays by bringing computation close to data.…”

Section: Overview and Related Workmentioning

confidence: 99%

CG-OoO

Mohammadi

Aamodt

Dally

2017

ACM Trans. Archit. Code Optim.

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We introduce the Coarse-Grain Out-of-Order (CG-OoO) general-purpose processor designed to achieve close to In-Order (InO) processor energy while maintaining Out-of-Order (OoO) performance. CG-OoO is an energy-performance-proportional architecture. Block-level code processing is at the heart of this architecture; CG-OoO speculates, fetches, schedules, and commits code at block-level granularity. It eliminates unnecessary accesses to energy-consuming tables and turns large tables into smaller, distributed tables that are cheaper to access. CG-OoO leverages compiler-level code optimizations to deliver efficient static code and exploits dynamic block-level and instruction-level parallelism. CG-OoO introduces Skipahead, a complexity effective, limited out-of-order instruction scheduling model. Through the energy efficiency techniques applied to the compiler and processor pipeline stages, CG-OoO closes 62% of the average energy gap between the InO and OoO baseline processors at the same area and nearly the same performance as the OoO. This makes CG-OoO 1.8× more efficient than the OoO on the energy-delay product inverse metric. CG-OoO meets the OoO nominal performance while trading off the peak scheduling performance for superior energy efficiency.

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“…None of they use low-level dataflow to address memory access. Nowatzki et al argue for a paradigm of fine-grained hybrid dataflow execution to get benefits of OOO and dataflow [51], and MAD is one such instance.…”

Section: Related Workmentioning

confidence: 99%

Efficient execution of memory access phases using dataflow specialization

Kim

Sankaralingam

2015

SIGARCH Comput. Archit. News

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This paper identifies a new opportunity for improving the efficiency of a processor core: memory access phases of programs. These are dynamic regions of programs where most of the instructions are devoted to memory access or address computation. These occur naturally in programs because of workload properties, or when employing an in-core accelerator, we get induced phases where the code execution on the core is access code. We observe such code requires an OOO core's dataflow and dynamism to run fast and does not execute well on an in-order processor. However, an OOO core consumes much power, effectively increasing energy consumption and reducing the energy efficiency of in-core accelerators.We develop an execution model called memory access dataflow (MAD) that encodes dataflow computation, eventcondition-action rules, and explicit actions. Using it we build a specialized engine that provides an OOO core's performance but at a fraction of the power. Such an engine can serve as a general way for any accelerator to execute its respective induced phase, thus providing a common interface and implementation for current and future accelerators. We have designed and implemented MAD in RTL, and we demonstrate its generality and flexibility by integration with four diverse accelerators (SSE, DySER, NPU, and C-Cores). Our quantitative results show, relative to in-order, 2-wide OOO, and 4-wide OOO, MAD provides 2.4×, 1.4× and equivalent performance respectively. It provides 0.8×, 0.6× and 0.4× lower energy.

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Exploring the potential of heterogeneous von neumann/dataflow execution models

Cited by 13 publications

References 34 publications

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays

Inter-Thread Communication in Multithreaded, Reconfigurable Coarse-Grain Arrays

CG-OoO

Efficient execution of memory access phases using dataflow specialization

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