Exploring the Performance Limits of Out-of-order Commit

Alipour, Mehdi; Carlson, Trevor E.

doi:10.1145/3075564.3075581

Cited by 10 publications

(11 citation statements)

References 10 publications

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“…Our work confirms previous studies [2,5,21] that the least aggressive core benefits the most from least aggressive out-of-order commit and in addition, by introducing a taxonomy, for the first time we show that more aggressive cores gain more, comparatively, from aggressive out-of-order commit. All in all, our study shows that as a future direction, not only safe but also unsafe out-of-order commit appears to be very promising.…”

Section: Analyzes Performedsupporting

confidence: 90%

“…Figure 13 shows the potential for performance improvement from relaxing the out-of-order commit conditions across the three architectures for both safe and unsafe out-of-ordercommit. As has been seen previously [2,5,21], the least aggressive out-of-order commit configuration (safe OOC with a commit depth of 4) is most beneficial for the least aggressive out-of-order processor, SLM (compare the leftmost bars of Fig. 13a-c).…”

Section: Analysis Of Cpu Aggressivenesssupporting

confidence: 62%

“…Section 4 provides a detailed performance analysis for each out-of-order commit condition, both from the point of view of aggressive and reluctant out-of-order commit. In Sections 5 and 6 we compare the early release of physical register and memory hierarchy parallelism, respectively, with Out-of-Order commit; extending previous work [2]. Finally, the related works and conclusion are presented in Sections 7 and 8 respectively.…”

Section: Resultsmentioning

confidence: 91%

“…Today, significantly improving single-thread performance in an energy-efficient manner remains a challenge. The goal of this work is to help researchers to hone in on the most profitable aspects of OOC by offering: i) a detailed exploration of the limits of out-of-order commit conditions and ii) a taxonomy for out-of-order commit [2].…”

Section: Why We Do Itmentioning

confidence: 99%

“…To address this resource constraint, techniques such as delayed allocation and Rarly Release of the Physical Register (ERPR) [23] have been developed. In this section, we compare ERPR with the OOC taxonomy [2].…”

Section: Early Release Of Physical Registers Vs Out-of-order Commitmentioning

confidence: 99%

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Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit

Alipour

Carlson

Black-Schaffer

2018

J Sign Process Syst

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Out-of-order execution is essential for high performance, general-purpose computation, as it can find and execute useful work instead of stalling. However, it is typically limited by the requirement of visibly sequential, atomic instruction execution-in other words, in-order instruction commit. While in-order commit has a number of advantages, such as providing precise interrupts and avoiding complications with the memory consistency model, it requires the core to hold on to resources (reorder buffer entries, load/store queue entries, physical registers) until they are released in program order. In contrast, out-of-order commit can release some resources much earlier, yielding improved performance and/or lower resource requirements. Non-speculative out-of-order commit is limited in terms of correctness by the conditions described in the work of Bell and Lipasti (2004). In this paper we revisit out-of-order commit by examining the potential performance benefits of lifting these conditions one by one and in combination, for both non-speculative and speculative out-of-order commit. While correctly handling recovery for all out-of-order commit conditions currently requires complex tracking and expensive checkpointing, this work aims to demonstrate the potential for selective, speculative out-of-order commit using an oracle implementation without speculative rollback costs. Through this analysis of the potential of out-of-order commit, we learn that: a) there is significant untapped potential for aggressive variants of out-of-order commit; b) it is important to optimize the out-of-order commit depth for a balanced design, as smaller cores benefit from reduced depth while larger cores continue to benefit from deeper designs; c) the focus on implementing only a subset of the out-of-order commit conditions could lead to efficient implementations; d) the benefits of out-of-order commit increases with higher memory latency and in conjunction with prefetching; e) out-of-order commit exposes additional parallelism in the memory hierarchy.

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Section: Analyzes Performedsupporting

confidence: 90%

Section: Analysis Of Cpu Aggressivenesssupporting

confidence: 62%

Section: Resultsmentioning

confidence: 91%

Section: Why We Do Itmentioning

confidence: 99%

Section: Early Release Of Physical Registers Vs Out-of-order Commitmentioning

confidence: 99%

See 3 more Smart Citations

Maximizing Limited Resources: a Limit-Based Study and Taxonomy of Out-of-Order Commit

Alipour

Carlson

Black-Schaffer

2018

J Sign Process Syst

Self Cite

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Seeds of SEED: Preventing Priority Inversion in Instruction Scheduling to Disrupt Speculative Interference

Sakalis

Själander

2021

2021 International Symposium on Secure and Private Execution Environment Design (SEED)

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Speculative side-channel attacks consist of two parts: The speculative instructions that abuse speculative execution to gain illegal access to sensitive data and the side-channel instructions that leak the sensitive data. Typically, the side-channel instructions are assumed to follow the speculative instructions and be dependent on them. Speculative side-channel defenses have taken advantage of these facts to construct solutions where speculative execution is limited only under the presence of these conditions, in an effort to limit the performance overheads introduced by the defense mechanisms.Unfortunately, it turns out that only focusing on dependent instructions enables a new set of attacks, referred to as "speculative interference attacks". These are a new variant of speculative side-channel attacks, where the side-channel instructions are placed before the point of misspeculation and hence before any illegal speculative instructions. As this breaks the previous assumptions on how speculative side-channel attacks work, this new attack variant can be used to bypass many of the existing defenses.We argue that the root cause of speculative interference is a priority inversion between the scheduling of older, bound to be committed, and younger, bound to be squashed instructions, which affects the execution order of the former. This priority inversion can be caused by affecting either the readiness of a not-yet-ready older instruction or the issuing priority of an older instruction after it becomes ready. We disrupt the opportunity for speculative interference by ensuring that current defenses adequately prevent the interference of younger instructions with the availability of operands to older instructions and by proposing an instruction scheduling policy to preserve the priority of ready instructions. As a proof of concept, we also demonstrate how the prevention of scheduling-priority inversion can safeguard a specific defense, Delayon-Miss, from the possibility of speculative interference attacks. We first discuss why it is susceptible to interference attacks and how this can be corrected without introducing any additional performance costs or hardware complexity, with simple instruction scheduling rules.

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