Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs

Sanchez, Alberto; Todorovich, Elías; Castro, Ángel de

doi:10.3390/electronics7100219

Cited by 17 publications

(14 citation statements)

References 34 publications

(42 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…The data-adaptive approach can also be implemented with a single barrel-shifter at the end of a standard 4-stage CIC architecture, however, this approach would require more FPGA resources. Floating point mathematical calculations [35][36][37] would grant even better performance. However, although recent high-end FPGAs integrates floating-point hard-processors, the resources needed are by far higher than those employed in the proposed solution.…”

Section: Discussionmentioning

confidence: 99%

Data-Adaptive Coherent Demodulator for High Dynamics Pulse-Wave Ultrasound Applications

Ricci

Meacci

2018

Electronics

View full text Add to dashboard Cite

Pulse-Wave Doppler (PWD) ultrasound has been applied to the detection of blood flow for a long time; recently the same method was also proven effective in the monitoring of industrial fluids and suspensions flowing in pipes. In a PWD investigation, bursts of ultrasounds at 0.5–10 MHz are periodically transmitted in the medium under test. The received signal is amplified, sampled at tens of MHz, and digitally processed in a Field Programmable Gate Array (FPGA). First processing step is a coherent demodulation. Unfortunately, the weak echoes reflected from the fluid particles are received together with the echoes from the high-reflective pipe walls, whose amplitude can be 30–40 dB higher. This represents a challenge for the input dynamics of the system and the demodulator, which should clearly detect the weak fluid signal while not saturating at the pipe wall components. In this paper, a numerical demodulator architecture is presented capable of auto-tuning its internal dynamics to adapt to the feature of the actual input signal. The proposed demodulator is integrated into a system for the detection of the velocity profile of fluids flowing in pipes. Simulations and experiments with the system connected to a flow-rig show that the data-adaptive demodulator produces a noise reduction of at least of 20 dB with respect to different approaches, and recovers a correct velocity profile even when the input data are sampled at 8 bits only instead of the typical 12–16 bits.

show abstract

Section: Discussionmentioning

confidence: 99%

Data-Adaptive Coherent Demodulator for High Dynamics Pulse-Wave Ultrasound Applications

Ricci

Meacci

2018

Electronics

View full text Add to dashboard Cite

show abstract

“…These equations can be programmed using any commercial software and using different numerical representations. In this paper, the use of fixed-point representation is strongly recommended since the implementation of a floating-point number in the FPGA is very resource-demanding [26].…”

Section: Solving the System Using A Numerical Methods (Step Three)mentioning

confidence: 99%

Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA

Estrada¹,

Vázquez

Vaquero

et al. 2020

Energies

Self Cite

View full text Add to dashboard Cite

Nowadays, the use of the hardware in the loop (HIL) simulation has gained popularity among researchers all over the world. One of its main applications is the simulation of power electronics converters. However, the equipment designed for this purpose is difficult to acquire for some universities or research centers, so ad-hoc solutions for the implementation of HIL simulation in low-cost hardware for power electronics converters is a novel research topic. However, the information regarding implementation is written at a high technical level and in a specific language that is not easy for non-expert users to understand. In this paper, a systematic methodology using LabVIEW software (LabVIEW 2018) for HIL simulation is shown. A fast and easy implementation of power converter topologies is obtained by means of the differential equations that define each state of the power converter. Five simple steps are considered: designing the converter, modeling the converter, solving the model using a numerical method, programming an off-line simulation of the model using fixed-point representation, and implementing the solution of the model in a Field-Programmable Gate Array (FPGA). This methodology is intended for people with no experience in the use of languages as Very High-Speed Integrated Circuit Hardware Description Language (VHDL) for Real-Time Simulation (RTS) and HIL simulation. In order to prove the methodology’s effectiveness and easiness, two converters were simulated—a buck converter and a three-phase Voltage Source Inverter (VSI)—and compared with the simulation of commercial software (PSIM® v9.0) and a real power converter.

show abstract

“…Electronics 2020, 9, x FOR PEER REVIEW 2 of 12 our design, the number representation in the signals plays a very important role. As has been previously studied by Sanchez et al [20], the fixed-point method is the perfect number representation method to optimize the integration step and area, due to the possibility of adjusting the number of bits for every signal, although this implies a higher time design than in the floating-point method [18,21,22]. Sanchez et al made a comparison among different representation methods, namely floattype and fixed-point methods, implementing a HIL model for a digital converter.…”

Section: Application Examplementioning

confidence: 99%

“…The hardware platforms that can reach these real-time emulations are the field programmable gate arrays (FPGAs) [11][12][13]. As such, in the last years the use of FPGAs with HIL models has increased [14][15][16][17][18][19].…”

Section: Introductionmentioning

confidence: 99%

Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters

et al. 2019

Self Cite

View full text Add to dashboard Cite

One of the main techniques for debugging power converters is hardware-in-the-loop (HIL), which is used for real-time emulation. Field programmable gate arrays (FPGA) are the most common design platforms due to their acceleration capability. In this case, the widths of the signals have to be carefully chosen to optimize the area and speed. For this purpose, fixed-point arithmetic is one of the best options because although the design time is high, it allows the personalization of the number of bits in every signal. The representation of state variables in power converters has been previously studied, however other signals, such as feedback signals, can also have a big influence because they transmit the value of one state variable to the rest, and vice versa. This paper presents an analysis of the number of bits in the feedback signals of a boost converter, but the conclusions can be extended to other power converters. The purpose of this work is to study how many bits are necessary in order to avoid the loss of information, but also without wasting bits. Errors of the state variables are obtained with different sizes of feedback signals. These show that the errors in each state variable have similar patterns. When the number of bits increases, the error decreases down to a certain number of bits, where an almost constant error appears. However, when the bits decrease, the error increases linearly. Furthermore, the results show that there is a direct relation between the number of bits in feedback signals and the inputs of the converter in the global error. Finally, a design criterion is given to choose the optimum width for each feedback signal, without wasting bits.

show abstract

Exploring the Limits of Floating-Point Resolution for Hardware-In-the-Loop Implemented with FPGAs

Cited by 17 publications

References 34 publications

Data-Adaptive Coherent Demodulator for High Dynamics Pulse-Wave Ultrasound Applications

Data-Adaptive Coherent Demodulator for High Dynamics Pulse-Wave Ultrasound Applications

Real-Time Hardware in the Loop Simulation Methodology for Power Converters Using LabVIEW FPGA

Analysis of Resolution in Feedback Signals for Hardware-in-the-Loop Models of Power Converters

Contact Info

Product

Resources

About