Exploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs

Purkayastha, Arnab A; Raghavendran, Sai; Thiagarajan, Jhanani; Tabkhi, Hamed

doi:10.1109/hpec.2019.8916236

2019 IEEE High Performance Extreme Computing Conference (HPEC) 2019

DOI: 10.1109/hpec.2019.8916236

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Exploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs

Arnab A Purkayastha

Sai Raghavendran

Jhanani Thiagarajan

et al.

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Cited by 4 publications

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A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

Mohammed,

Amir,

Ahmad

et al. 2023

2023 IEEE International Conference on Advanced Systems and Emergent Technologies (IC_ASET)

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Exploring the Efficiency of OpenCL Pipe for Hiding Memory Latency on Cloud FPGAs

Cited by 4 publications

References 25 publications

A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

A Review on Implementation of AES Algorithm Using Parallelized Architecture on FPGA Platform

Design Study on Impact of Memory Access Parallelism for Cloud FPGAs

A Code Transformation to Improve the Efficiency of OpenCL Code on FPGA through Pipes

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