Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Dimitroulakos, Gregory; Galanis, Michalis D.; Goutis, C.E.

doi:10.1109/ipdps.2006.1639349

Cited by 11 publications

(21 citation statements)

References 20 publications

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“…Mainly due to lack of the program counter, the control logic in most existing CGRA templates (e.g., [5], [21], [26]) is not as versatile to fully support various conditional execution features as in ordinary microprocessors. Therefore, in order to execute a kernel loop, we transform all branches, such as if-statements, within the original loop into predicate statements [20].…”

Section: A Predicationmentioning

confidence: 99%

A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures

Yoon

Shrivastava

Park

et al. 2009

IEEE Trans. VLSI Syst.

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Recently coarse-grained reconfigurable architectures (CGRAs) have drawn increasing attention due to their efficiency and flexibility. While many CGRAs have demonstrated impressive performance improvements, the effectiveness of CGRA platforms ultimately hinges on the compiler. Existing CGRA compilers do not model the details of the CGRA, and thus they are i) unable to map applications, even though a mapping exists, and ii) using too many processing elements (PEs) to map an application. In this paper, we model several CGRA details, e.g., irregular CGRA topologies, shared resources and routing PEs in our compiler and develop a graph drawing based approach, Split-Push Kernel Mapping (SPKM), for mapping applications onto CGRAs. On randomly generated graphs our technique can map on average 4.5 more applications than the previous approach, while generating mappings which have better qualities in terms of utilized CGRA resources. Utilizing fewer resources is directly translated into increased opportunities for novel power and performance optimization techniques. Our technique shows less power consumption in 71 cases and shorter execution cycles in 66 cases out of 100 synthetic applications, with minimum mapping time overhead. We observe similar results on a suite of benchmarks collected from Livermore loops, Mediabench, Multimedia, Wavelet and DSPStone benchmarks. SPKM is not a customized algorithm only for a specific CGRA template, and it is demonstrated by exploring various PE interconnection topologies and shared resource configurations with SPKM.

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Section: A Predicationmentioning

confidence: 99%

A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures

Yoon

Shrivastava

Park

et al. 2009

IEEE Trans. VLSI Syst.

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“…That is, variables with data reuse opportunities are stored and transferred through the CGRA's interconnection network instead of using the buses. The advantage of this technique has been evaluated in [16]. Additionally, each PE consists of one Reconfigurable Functional Unit (RFU), which it can be configured to perform a specific word-level operation in every cycle.…”

Section: Cgra Architecture Descriptionmentioning

confidence: 99%

“…Also, by increasing the size of the register files, the number of variables that can be cached internally in the 2D-grid of PEs is increased. Hence, the bus is relieved from unnecessary accesses [16]. The aforementioned changes have a positive impact on the value of IPC, however, by increasing the size and number of ports of the register files, the area together with the critical path also increases leading to lower clock frequency.…”

Section: Cgra Architecture Evaluationmentioning

confidence: 99%

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Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

et al. 2008

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Coarse Grain Reconfigurable Array (CGRA) architectures have been extensively used for accelerating time consuming loops. The design of such systems requires good balance between the architecture abilities and the loops' characteristics. A reliable design is characterized by optimized cost-performance trade-off. The main target of this paper is to present an exploration framework that automates the evaluation of CGRA architectures. In specific, the framework helps the designer to identify CGRA architectures tuned toward a specific application domain. The whole process is assisted: (1) by an optimized retargetable compiler based on modulo scheduling and (2) by the Synopsys Design Compiler that provides realization metrics such as the area and clock frequency. Both target on the description of a parametric CGRA architecture template which is capable of instantiating a large diversity of these architectures. Until now, many studies suggest that clock frequency influences performance. However, none of them examines the impact of architecture on clock frequency and performance. Our work studies in a unified way for the first time the area, the clock frequency, the instructions per cycle and performance. Hence, architectures with good compromise between cost and performance can be identified. Another objective of the paper is to present the advances made to the compiler approach used by the exploration framework. In specific, a new more effective priority scheme is proposed while the modulo scheduler has been equipped with backtracking capability. The experiments outline the algorithm's efficiency and scalability for a given set of DSP benchmarks. Moreover, optimized architectures with respect to cost-performance trade-off have been identified by an exploration over 72 CGRA architecture alternatives.

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“…This framework consists of: 1) an existing retargetable mapping methodology [7] based on a modulo scheduling technique and 2) by a parametric CGRA architecture template that has been described in hardware description language (VHDL). The latter is used for estimating the clock frequency and the area of each considered architecture instance using the Synopsis Design Compiler in the 0.13μm process of ASIC technology.…”

Section: Introductionmentioning

confidence: 99%

A unified evaluation framework for coarse grained reconfigurable array architectures

Dimitroulakos

Galanis

Kostaras

et al. 2007

Proceedings of the 4th International Conference on Computing Frontiers

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The efficiency of a coarse grained reconfigurable array architecture in terms of performance and hardware cost is hard to be determined. The large number of parameters that define an architecture instance and the mapping complexity makes the evaluation extremely difficult to accomplish without tool assistance. This paper investigates the four factors that are directly related with the efficiency of these architectures namely; the area, the clock frequency, the scheduling efficiency and performance. A unified exploration framework has been build for estimating the values of the 4 aforementioned factors for different architecture alternatives. The exploration framework consists of two parts: a) an existing retargetable compiler from which the mapping efficiency is estimated and b) from the parametric realization of the coarse grained reconfigurable array in hardware description language (VHDL). The latter is used for the estimation of the area and clock frequency of each architecture instance with the realization of the system in the 0.13μm process of ASIC technology. Also, the experiments refer to different architecture instances in terms of the processing elements' interconnection network, the register files' size, their number of input output ports, and finally the available bandwidth. Totally 72 architecture scenarios have been studied revealing how each characteristic influences performance and area for efficiently make design decisions.

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Exploring the design space of an optimized compiler approach for mesh-like coarse-grained reconfigurable architectures

Cited by 11 publications

References 20 publications

A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures

A Graph Drawing Based Spatial Mapping Algorithm for Coarse-Grained Reconfigurable Architectures

Compiler assisted architectural exploration framework for coarse grained reconfigurable arrays

A unified evaluation framework for coarse grained reconfigurable array architectures

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