Exploring speculative parallelism in SPEC2006

Packirisamy, Venkatesan; Zhai, Antonia; Hsu, Wei-Chung; Yew, Pen-Chung; Ngai, Tin-Fook

doi:10.1109/ispass.2009.4919640

Cited by 37 publications

(30 citation statements)

References 19 publications

(29 reference statements)

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“…A study involving manual parallelization of the SPEC2006 benchmarks for a TLS platform has been conducted in [18]. This study confirms the "conventional wisdom" that these benchmarks are 'difficult to parallelize' using traditional parallelizing compilers (Intel's ICC compiler in this case).…”

Section: Related Worksupporting

confidence: 54%

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Limits of region-based dynamic binary parallelization

Koch

Franke

2013

SIGPLAN Not.

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Efficiently executing sequential legacy binaries on chip multiprocessors (CMPs) composed of many, small cores is one of today's most pressing problems. Single-threaded execution is a suboptimal option due to CMPs' lower single-core performance, while multithreaded execution relies on prior parallelization, which is severely hampered by the low-level binary representation of applications compiled and optimized for a single-core target. A recent technology to address this problem is Dynamic Binary Parallelization (DBP), which creates a Virtual Execution Environment (VEE) taking advantage of the underlying multicore host to transparently parallelize the sequential binary executable. While still in its infancy, DBP has received broad interest within the research community. The combined use of DBP and thread-level speculation (TLS) has been proposed as a technique to accelerate legacy uniprocessor code on modern CMPs. In this paper, we investigate the limits of DBP and seek to gain an understanding of the factors contributing to these limits and the costs and overheads of its implementation. We have performed an extensive evaluation using a parameterizable DBP system targeting a CMP with light-weight architectural TLS support. We demonstrate that there is room for a significant reduction of up to 54% in the number of instructions on the critical paths of legacy SPEC CPU2006 benchmarks. However, we show that it is much harder to translate these savings into actual performance improvements, with a realistic hardware-supported implementation achieving a speedup of 1.09 on average.

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Section: Related Worksupporting

confidence: 54%

“…These benchmarks are widely used and regarded as typical for a broad range of application domains. They are sequential applications and have been described as difficult to parallelize using existing automated compiler-based methods [18]. The benchmarks were compiled using arc-gcc-4.2.1 with -O2 optimization level.…”

Section: Benchmarksmentioning

confidence: 99%

Limits of region-based dynamic binary parallelization

Koch

Franke

2013

SIGPLAN Not.

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“…GPGPU [1] [2] [3], OpenCL [4], CUDA [5], OpenMP [6]. Among those efforts, some researchers find Speculative MultiThreading (SpMT) an attractive approach as it will automatically extract parallelism from serial programs without programmer's extra efforts [7] [8] [9] [10].…”

Section: Introductionmentioning

confidence: 99%

Offline Data Dependence Analysis to Facilitate Runtime Parallelism Extraction

Chen²,

Chen

et al. 2014

2014 IEEE 17th International Conference on Computational Science and Engineering

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In the era of multi-core processors, it is increasingly important to extract parallelism from programs. A key work to find and extract parallelism is data dependence analysis. This paper proposes to analyze the data dependences among code blocks offline, so as to save the computing time and resources with runtime execution.Offline data dependence analysis is feasible because register numbers to access are usually directly encoded in instructions, and register accesses are way more frequent than memory accesses. Therefore we may parse an executable file, divide it into code blocks, and find their register read/write dependences, which can be used at runtime to accelerate future executions.The offline analysis is more than mere static analysis, because many implicit dependences are only revealed at runtime. So we will simulate a runtime environment to analyze the simulated execution, which helps to better understand the dependences, and facilitate runtime parallelization.We built a trace driven simulator and conducted experiments with SPEC2006 benchmarks. The data shows that compared with online analysis, for every 1000 instructions the offline analysis will be able to save at least 1420 ∼ 2332 clocks of time (i.e. 1.42 ∼ 2.33 times of performance improvement), plus other additional 13 ∼ 32 clocks of time (i.e. 1.3% ∼ 3.2% of performance improvement), or equivalent computing resource.

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“…Speculative Multi-Threading (SpMT) (a.k.a Thread Level Speculation, or TLS) [4] [5], parallel languages [6], etc. Such researches date back to decades ago, but few pragmatic results were obtained as the speedup were rather limited.…”

Section: Introductionmentioning

confidence: 99%

Exploring Potential Parallelism of Sequential Programs with Superblock Reordering

Chen

2012

2012 IEEE 14th International Conference on High Performance Computing and Communication &Amp; 2012 IEEE 9th International Confe

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The growing number of processing cores in a single CPU is demanding more parallelism from sequential programs. But in the past decades few work has succeeded in automatically exploiting enough parallelism, which casts a shadow over the many-core architecture and the automatic parallelization research. However, actually few work was tried to understand the nature, inner structure, or amount, of the potentially available parallelism in programs.In this paper we will try to analyze at runtime the dynamic data dependencies among superblocks of sequential programs. We designed a Meta Reorder Buffer (Meta-RB) to measure and exploit the available parallelism, with which the superblocks are dynamically analyzed, reordered and dispatched to run in parallel on an ideal many-core processor, and the data dependencies and program correctness are still maintained.In our experiments, we observed that with the superblock reordering, the potential speedup ranged from 1.627 to 95.275, and reached 22.852 on average. The results shows that the potential parallelism of normal programs is still far from fully exploited by existing technologies, which makes the automatic parallelization a promising research direction for many-core architectures.

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Exploring speculative parallelism in SPEC2006

Cited by 37 publications

References 19 publications

Limits of region-based dynamic binary parallelization

Limits of region-based dynamic binary parallelization

Offline Data Dependence Analysis to Facilitate Runtime Parallelism Extraction

Exploring Potential Parallelism of Sequential Programs with Superblock Reordering

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