Exploring High-Level Neural Networks Architectures for Efficient Spiking Neural Networks Implementation

Islam, Riadul; Majurski, Patrick; Kwon, Jun Soo; Tummala, Sri Ranga Sai Krishna

doi:10.1109/icrest57604.2023.10070080

Cited by 2 publications

(16 citation statements)

References 18 publications

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“…This statistical measure was utilized to compare the activations in ANNs with the spike rates in SNNs. Figure 3 provides a graphical representation of the correlation coefficients for each layer of the CNN_mnist network [ 3 ]. This network was specifically trained using the mnist dataset, and the coefficients presented are the averages calculated over all the data batches [ 3 ].…”

Section: Resultsmentioning

confidence: 99%

“…The novel SNN graph-partitioning algorithm (SNN-GPA), as delineated in Algorithm 1, presents a structured methodology for neural network partitioning [ 3 ]. The SNN-GPA accepts three key inputs: an SNN represented as a graph ( G ), the specified number of clusters ( N ), and the total number of layers ( n ).…”

Section: Proposed Spiking Neural Network Implementation Tool Flowmentioning

confidence: 99%

“…These challenges include (i) a dearth of comprehensive guidelines for constructing a software-level model translating to hardware deployment, (ii) the absence of design-automation devices and the imperative need for a breadth of domain expertise, and (iii) limitations in existing neuron clustering approaches, which are incapable of handling a large number of neurons in an SNN. This research addresses the aforementioned challenges by offering an existing graph-partitioning algorithm [ 3 ] and effectuating the placement of SNN architectures onto an NoC model, employing a methodology of a generic nature.…”

Section: Introductionmentioning

confidence: 99%

“…In this manuscript, we address a significant limitation present in current graph-partitioning algorithms [ 1 , 4 , 5 ], specifically the constraint on the number of vertices, which typically remains below 10,000. We introduce our novel greedy graph-partitioning algorithm, which has the capacity to effectively manage graphs comprising over 100,000 vertices, thereby mitigating a substantial amount of communication overhead when integrated into crossbar hardware configurations [ 3 ]. In particular, the key contributions of this work are as follows: We introduce our novel design and automation methodology that systematically transforms any neural network architecture into an SNN for the purpose of optimizing energy efficiency in neuromorphic computations.…”

Section: Introductionmentioning

confidence: 99%

“…However, a notable limitation of existing graph-partitioning methodologies, as discussed in previous works [ 1 , 4 , 5 ], is their inability to efficiently process graphs with more than 10K vertices. The present study utilized our novel SNN graph-partitioning algorithm (SNN-GPA) to address this constraint [ 3 ]. This algorithm demonstrates a marked capability in handling graphs containing in excess of 100,000 vertices.…”

Section: Introductionmentioning

confidence: 99%

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Benchmarking Artificial Neural Network Architectures for High-Performance Spiking Neural Networks

Islam,

Majurski,

Kwon

et al. 2024

Sensors

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Organizations managing high-performance computing systems face a multitude of challenges, including overarching concerns such as overall energy consumption, microprocessor clock frequency limitations, and the escalating costs associated with chip production. Evidently, processor speeds have plateaued over the last decade, persisting within the range of 2 GHz to 5 GHz. Scholars assert that brain-inspired computing holds substantial promise for mitigating these challenges. The spiking neural network (SNN) particularly stands out for its commendable power efficiency when juxtaposed with conventional design paradigms. Nevertheless, our scrutiny has brought to light several pivotal challenges impeding the seamless implementation of large-scale neural networks (NNs) on silicon. These challenges encompass the absence of automated tools, the need for multifaceted domain expertise, and the inadequacy of existing algorithms to efficiently partition and place extensive SNN computations onto hardware infrastructure. In this paper, we posit the development of an automated tool flow capable of transmuting any NN into an SNN. This undertaking involves the creation of a novel graph-partitioning algorithm designed to strategically place SNNs on a network-on-chip (NoC), thereby paving the way for future energy-efficient and high-performance computing paradigms. The presented methodology showcases its effectiveness by successfully transforming ANN architectures into SNNs with a marginal average error penalty of merely 2.65%. The proposed graph-partitioning algorithm enables a 14.22% decrease in inter-synaptic communication and an 87.58% reduction in intra-synaptic communication, on average, underscoring the effectiveness of the proposed algorithm in optimizing NN communication pathways. Compared to a baseline graph-partitioning algorithm, the proposed approach exhibits an average decrease of 79.74% in latency and a 14.67% reduction in energy consumption. Using existing NoC tools, the energy-latency product of SNN architectures is, on average, 82.71% lower than that of the baseline architectures.

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Section: Resultsmentioning

confidence: 99%

Section: Proposed Spiking Neural Network Implementation Tool Flowmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%