Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework

Gilabert, Francisco Jurado; Medardoni, Simone; Bertozzi, Davide; Benini, Luca; Gomez, Maria E.; López, Pedro; Duato, J.

doi:10.1109/nocs.2008.4492730

Cited by 26 publications

(21 citation statements)

References 45 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Moreover, the critical path scales quite smoothly for the realistic cases analysed in Fig.6-a. As suggested by [24], realistic target frequencies for the OCP section of the system might be around 500 MHz, while the network could be operated at 1 GHz. By synthesizing the NI initiator under these conditions, the critical path of its OCP frontend is 1.30ns and goes to the SData output.…”

Section: Synthesis Resultsmentioning

confidence: 99%

“…The work in [19] trades-off the number of dimensions with the number of cores per router, but lacks of physical insights. Physical implications and feasibility of multi-dimensional and/or concentrated topologies have been investigated in [24].…”

Section: Previous Workmentioning

confidence: 99%

“…In practice, since we are focusing on video decoding, the amount of write data will be much higher than that of read data. We set the network clock frequency to be twice the frequency of the OCP section, which is a reasonable assumption for the xpipes architecture [24].…”

Section: Application-specific Topologymentioning

confidence: 99%

See 2 more Smart Citations

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Ferrante

Medardoni

Bertozzi

2008

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

Self Cite

View full text Add to dashboard Cite

show abstract

Section: Synthesis Resultsmentioning

confidence: 99%

Section: Previous Workmentioning

confidence: 99%

See 1 more Smart Citation

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Ferrante

Medardoni

Bertozzi

2008

2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools

Self Cite

View full text Add to dashboard Cite

show abstract

“…Nevertheless, other options, like topologies with more than two dimensions, or fat-trees may be very attractive for NoCs. In the first case, multidimensional topologies result in reduced packet latency because of the smaller number of hops required to reach a given destination [14]. Additionally, this effect is more noticeable when combining topologies with more than two dimensions with an increment in the number of cores per switch.…”

Section: Network-on-chip Architecturementioning

confidence: 99%

Explicit Communication and Synchronization in SARC

et al. 2010

View full text Add to dashboard Cite

SARC merges cache controller and network interface functions by relying on a single hardware primitive: each access checks the tag and the state of the addressed line for possible occurrence of events that may trigger responses like coherence actions, RDMA, synchronization, or configurable event notifications. The fully virtualized and protected user-level API is based on specially marked lines in the scratchpad space that respond as command buffers, counters, or queues. The runtime system maps communication abstractions of the programming model to data transfers among local memories using remote write or read DMA and into task synchronization and scheduling using notifications, counters, and queues. The on-chip network provides efficient communication among these configurable memories, using advanced topologies and routing algorithms, and providing for process variability in NoC links. We simulate benchmark kernels on a full-system simulator to compare speedup and network traffic against cache-only systems with directory-based coherence and prefetchers. Explicit communication provides 10 to 40% higher speedup on 64 cores, and reduces network traffic by factors of 2 to 4, thus economizing on energy and power; lock and barrier latency is reduced by factors of 3 to 5. EXPLICIT COMMUNICATION AND NETWORK INTERFACE EVOLUTIONInterprocessor communication (IPC) is the basis of parallel processing. IPC can be implicit, when the addresses supplied by the software do not identify physical data locations or (time of) movement, or it can be explicit, when software (the application, or compiler, or runtime system) is able to also indicate physical placement or transfers, besides specifying computation on data. The SARC architecture [1], supports both implicit IPC, through cache coherence, for ease of programming, and explicit IPC, through scratchpad memories and remote store instructions or remote DMA operations, to be used by software whenever possible for achieving scalable performance.In order to hide IPC latency, when using implicit communication, we need large issue windows in out-of-order-execution processors, or sophisticated data prefetchers, or both. Explicit communication has the potential to better hide IPC latency, in those cases when software knows better than hardware what transfers need to take place and when. Remote store instructions, to addresses that indicate proximity to the consumer, when that is known at production time, will transfer data at the earliest possible time; hardware should coalesce writes to adjacent targets into few network packets, and the processor should not wait for the arrival acknowledgments. Remote direct memory access (RDMA) is the other method for explicit communication, in cases that require either reads -when the consumer is unknown or unavailable at production time-or multi-word writes -to achieve good coalescence.Traditional systems viewed networks as external (slow) devices, provided DMA in the network interface (NI), and interacted to it through (slow) input/output (I...

show abstract

“…[33] to use high-dimensional topologies finding a trade-off between the number of cores per router and the delay of long links. In the same direction, the authors in [3] propose the use of an enhanced concentrated mesh architecture using replicated sub-networks and express channels.…”

Section: The Network-on-chip Paradigmmentioning

confidence: 99%

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Luz¹

View full text Add to dashboard Cite

ii AgradecimientosVarios han sido los años de mi vida que he dedicado a la realización de esta tesis. Durante estos años si bien he conseguido compaginar mi vida personal con el desarrollo de la la tesis, ha sido el doctorado el que ha marcado de algún modo u otro los tiempos en mi vida. Por todo esto y por mucho más agradezco a Anna la paciencia que durante todos estos años me ha mostrado. Sin su cariño y comprensión la realización de la tesis hubiera sido sin duda un proceso mucho más tortuoso. También aprovecho para agradecer a mis padres que en todo momento me incentivaran a llegar siempre lo más lejos posible en la formación académica. En numerosas ocasiones a lo largo de la tesis me he preguntado si todo esto realmente vale la pena. Ahora con perspectiva y la tesis bajo el brazo todo se ve distinto.Por otro lado me gustaría agradecer a Federico Silla, Vicente Santonja y José Duato la oportunidad que me brindaron para realizar el doctorado en Informática en el Grupo de Arquitecturas Paralelas. Quisiera agradecer especialmente a Fede la ayuda que me ha prestado durante estos años y que ha sido fundamental para la realización de la tesis.Aunque una tesis supone un importante sacrificio personal, no hay que obviar que para la realización de la misma he contado con la inestimable ayuda de muchos compañeros de laboratorio. Durante la etapa inicial de mi doctorado fueron Ricardo, Blas, Crispin, Gaspar, Andres, Paco, Hector, Rafa, David y Noel mis compañeros en el GAP. Con ellos he compartido buenos momentos dentro y fuera del laboratorio. Recuerdo con especial cariño las innumerables ocasiones en las que Hector y yo ( al principio con la compañía de David) maldijimos el día en el que decidimos hacer la tesis. Cinco años después esta etapa ha acabado y una nueva empieza en Barcelona. Más tarde iii iv la incorporación de Toni, con el que ya compartí buenos momentos en los trabajos de Microelectrónica de Teleco, ha sido un apoyo fundamental a la hora de afrontar los problemas que desde el lado oscuro, en el cual mi tesis se ha desarrollado, han ido surgiendo. Finalmente nuevos compañeros de laboratorio como Javi, Knut, Mario, Alberto... han hecho posible que el ambiente del laboratorio siga tan bueno como siempre.Porúltimo no podía olvidarme de agradecer a mis amigos; a los que son heavies y a los que son flamencos, a los que disfrutan de la escalada y a los playeros, a los de la facultad y a los que no han estudiado, que hayan hecho que el tiempo que ha durado la tesis pase tan rápido. Sin duda he disfrutado mucho durante todo este tiempo.

show abstract

Exploring High-Dimensional Topologies for NoC Design Through an Integrated Analysis and Synthesis Framework

Cited by 26 publications

References 45 publications

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Network Interface Sharing Techniques for Area Optimized NoC Architectures

Explicit Communication and Synchronization in SARC

Addressing Manufacturing Challenges in NoC-based ULSI Designs

Contact Info

Product

Resources

About