Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs

Gonçalves, Ana; Peres, Tiago; Véstias, Mário P.

doi:10.1007/978-3-030-17227-5_27

Cited by 6 publications

(5 citation statements)

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…During training, the data is typically in singleprecision floating-point format. For inference in FPGAs, the feature maps and kernels can be converted to fixed-point format with less precision, typically 8 or 16 bits, reducing the storage requirements, hardware utilisation and power consumption [23].…”

Section: B Object Detection With Yolomentioning

confidence: 99%

A Full Featured Configurable Accelerator for Object Detection With YOLO

et al. 2021

Self Cite

View full text Add to dashboard Cite

Object detection and classification is an essential task of computer vision. A very efficient algorithm for detection and classification is YOLO (You Look Only Once). We consider hardware architectures to run YOLO in real-time on embedded platforms. Designing a new dedicated accelerator for each new version of YOLO is not feasible given the fast delivery of new versions. This work's primary goal is to design a configurable and scalable core for creating specific object detection and classification systems based on YOLO, targeting embedded platforms. The core accelerates the execution of all the algorithm steps, including pre-processing, model inference and post-processing. It considers a fixed-point format, linearised activation functions, batch-normalisation, folding, and a hardware structure that exploits most of the available parallelism in CNN processing. The proposed core is configured for real-time execution of YOLOv3-Tiny and YOLOv4-Tiny, integrated into a RISC-V-based system-on-chip architecture and prototyped in an UltraScale XCKU040 FPGA (Field Programmable Gate Array). The solution achieves a performance of 32 and 31 frames per second for YOLOv3-Tiny and YOLOv4-Tiny, respectively, with a 16-bit fixed-point format. Compared to previous proposals, it improves the frame rate at a higher performance efficiency. The performance, area efficiency and configurability of the proposed core enable the fast development of real-time YOLO-based object detectors on embedded systems.

show abstract

Section: B Object Detection With Yolomentioning

confidence: 99%

A Full Featured Configurable Accelerator for Object Detection With YOLO

et al. 2021

Self Cite

View full text Add to dashboard Cite

show abstract

“…During training, the data are typically in single-precision floating-point format. For inference in FPGAs, the feature maps and kernels are usually converted to fixedpoint format with less precision, typically 8 or 16 bits, reducing the storage requirements, hardware utilization, and power consumption [23].…”

Section: Cnn Model Optimizationmentioning

confidence: 99%

Configurable Hardware Core for IoT Object Detection

et al. 2021

Self Cite

View full text Add to dashboard Cite

Object detection is an important task for many applications, like transportation, security, and medical applications. Many of these applications are needed on edge devices to make local decisions. Therefore, it is necessary to provide low-cost, fast solutions for object detection. This work proposes a configurable hardware core on a field-programmable gate array (FPGA) for object detection. The configurability of the core allows its deployment on target devices with diverse hardware resources. The object detection accelerator is based on YOLO, for its good accuracy at moderate computational complexity. The solution was applied to the design of a core to accelerate the Tiny-YOLOv3, based on a CNN developed for constrained environments. However, it can be applied to other YOLO versions. The core was integrated into a full system-on-chip solution and tested with the COCO dataset. It achieved a performance from 7 to 14 FPS in a low-cost ZYNQ7020 FPGA, depending on the quantization, with an accuracy reduction from 2.1 to 1.4 points of mAP50.

show abstract

“…Data quantization methods reduce the complexity of arithmetic operators and the number of bits (bitwidth) to represent parameters and activations. The complexity of hardware implementations of arithmetic operations depends on the type of data [112]. Operators for floating-point arithmetic are more complex than for fixed-point or integer arithmetic.…”

Section: Hardware-oriented Deep Neural Network Optimizationsmentioning

confidence: 99%

Moving Deep Learning to the Edge

et al. 2020

Self Cite

View full text Add to dashboard Cite

Deep learning is now present in a wide range of services and applications, replacing and complementing other machine learning algorithms. Performing training and inference of deep neural networks using the cloud computing model is not viable for applications where low latency is required. Furthermore, the rapid proliferation of the Internet of Things will generate a large volume of data to be processed, which will soon overload the capacity of cloud servers. One solution is to process the data at the edge devices themselves, in order to alleviate cloud server workloads and improve latency. However, edge devices are less powerful than cloud servers, and many are subject to energy constraints. Hence, new resource and energy-oriented deep learning models are required, as well as new computing platforms. This paper reviews the main research directions for edge computing deep learning algorithms.

show abstract

Exploring Data Size to Run Convolutional Neural Networks in Low Density FPGAs

Cited by 6 publications

References 16 publications

A Full Featured Configurable Accelerator for Object Detection With YOLO

A Full Featured Configurable Accelerator for Object Detection With YOLO

Configurable Hardware Core for IoT Object Detection

Moving Deep Learning to the Edge

Contact Info

Product

Resources

About