Exploring configurations of functional units in an out-of-order superscalar processor

Jourdan, Stéphan; Sainrat, Pascal; Litaize, Daniel

doi:10.1145/223982.224366

Cited by 19 publications

(5 citation statements)

References 6 publications

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“…One such economic problem is the power consumption of excess FUs, which must consume power even when not in use via static power dissipation. Previous research has been done to empirically derive optimal FU configurations via simulation [2]. Such approaches typically only examine the overall throughput of the processor to determine how well a particular configuration fits a processor, whereas our goal is to examine the pipeline effects of each configuration.…”

Section: Related Workmentioning

confidence: 99%

“…Clearly, in a system with bandwidth B between the IQ and the FUs, it would be optimal to have the number of each type of FU equal to B to fulfill its potential. In such a configuration, criteria (2) is always satisfied and we should intuitively expect higher throughput than a configuration with any fewer FUs. However, FUs are expensive in many dimensions, including economic cost, chip space, and idle power consumption.…”

Section: Introductionmentioning

confidence: 99%

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A queuing model for CPU functional unit and issue queue configuration

Carroll

Lin

2018

Simulation Modelling Practice and Theory

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In a superscalar processor, instructions of various types flow through an execution pipeline, traversing hardware resources which are mostly shared among many different instruction types. A notable exception to shared pipeline resources is the collection of functional units, the hardware that performs specific computations. In a trade-off of cost versus performance, a pipeline designer must decide how many of each type of functional unit to place in a processor's pipeline. In this paper, we model a superscalar processor's issue queue and functional units as a novel queuing network. We treat the issue queue as a finite-sized waiting area and the functional units as servers. In addition to common queuing problems, customers of the network share the queue but wait for specific servers to become ready (e.g., addition instructions wait for adders). Furthermore, the customers in this queue are not necessary ready for service, since instructions may be waiting for operands. In this paper we model a novel queuing network that provides a solution to the expected queue length of each type of instruction. This network and its solution can also be generalized to other problems, notably other resource-allocation issues that arise in superscalar pipelines.

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Section: Related Workmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

A queuing model for CPU functional unit and issue queue configuration

Carroll

Lin

2018

Simulation Modelling Practice and Theory

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“…Studies on the ideal mix and functionality of functional units in a superscalar processor have been performed [7]. These studies show that good gains can be obtained by increasing the number of identical functional units, as well as the types of instructions these units can execute.…”

Section: Proposed Modificationmentioning

confidence: 99%

Dynamic Reallocation of Functional Units in Superscalar Processors

Epalza

Ienne

Mlynek

2004

Advances in Computer Systems Architecture

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Abstract. In the context of general-purpose processing, an increasing number of diverse functional units are added to cover a wide spectrum of applications. However, it is still possible to design custom logic adapted to a particular application that will perform far better than a processor. In an attempt to give it some adaptability, adding some reconfigurability can help improve performance. We propose to extend the possibilities of complex multifunction units by dynamically reallocating existing complex functional units as multiple simpler units. The fact that more than one simple unit is involved in the "reconfiguration" process implies that the decision is more global and needs to be taken for a longer period of time. We show that in typical superscalar architectures, there are no major impediments to implementing such a decision scheme, and that on a specific reallocation opportunity we can achieve speedups of up to 56% over a mainstream superscalar processor and practically no losses.

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“…The baseline model is an out-of-order execute superscalar processor based on the register update unit[l8]. Following the discussion explained in [7], we decided the configuration of the baseline processor summarized in Table 1. The penalty for the data dependence misprediction is assumed to be 3 cycles.…”

Section: Processor Modelmentioning

confidence: 99%

Speculative resolution of ambiguous memory aliasing

Sato

1997

Proceedings Innovative Architecture for Future Generation High-Performance Processors and Systems

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The ambiguous memory aliasing is proposed to be speculatively resolved. A load instruction is speculatively executed with load address prediction, and its dependent instructions are speculatively executed. A store instruction is also speculatively resolved with store address prediction, and its dependent instructions are speculatively executed. From the experimental evaluation, we have found that this data speculation combining memory disambiguation with address prediction improves the performance of coming-generation superscalar processors b y up to 21.0%.

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Exploring configurations of functional units in an out-of-order superscalar processor

Cited by 19 publications

References 6 publications

A queuing model for CPU functional unit and issue queue configuration

A queuing model for CPU functional unit and issue queue configuration

Dynamic Reallocation of Functional Units in Superscalar Processors

Speculative resolution of ambiguous memory aliasing

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