Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

Siozios, Kostas; Sotiriadis, K.; Pavlidis, Vasilis F.; Sondris, D.

doi:10.1109/fpl.2007.4380738

Cited by 13 publications

(20 citation statements)

References 8 publications

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“…The reconfigurable unit located in i th position in the first coordinate (x), j th position in the second coordinate (y) and k th position in the third coordinate (z) is identified by coordinate (i, j, k), counted from the lower-leftmost coordinate (1,1,1), where 1 ≤ i ≤ W , 1 ≤ j ≤ H, and 1 ≤ k ≤ T H.…”

Section: Problem Definition a 3d Fpga Denoted By Fpga (W H T Hmentioning

confidence: 99%

“…Some of benefits of exploring 3D FPGAs compared to 2D FPGAs are reductions in wire-length [1], delay [1][2] [3], channel width [2], power dissipation [2][3], energy consumption [1], and an increase in logic density [3]. However, online task scheduling and placement algorithms for 3D FPGAs have not been well explored in literature.…”

Section: Introduction and Related Workmentioning

confidence: 99%

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A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Marconi

Mitra

2011

2011 International Conference on Field-Programmable Technology

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Abstract-The recent emergence of 3D partially reconfigurable FPGAs implies that we need efficient online hardware task scheduling and placement algorithms for such architectures. However, the algorithms available in the literature for 3D FPGAs create a "blocking-effect". That is, these algorithms tend to make a wrong decision in finding a location of each arriving hardware task during runtime scheduling and placement on 3D partially reconfigurable FPGAs. This leads to currently scheduled tasks blocking future hardware tasks from being scheduled and satisfying their deadlines. We need to solve this problem to maximize the performance of partially reconfigurable runtime systems implemented using 3D chip technology. We propose a novel placement and scheduling algorithm with a blocking-aware heuristic to make better decisions at runtime. Based on evaluation using both synthetic and real workloads, our algorithm reduces deadline miss rate by 61% with 15% longer runtime overhead compared to state-of-the-art algorithms.

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Section: Problem Definition a 3d Fpga Denoted By Fpga (W H T Hmentioning

confidence: 99%

Section: Introduction and Related Workmentioning

confidence: 99%

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Marconi

Mitra

2011

2011 International Conference on Field-Programmable Technology

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“…The adjacent pieces are connected to each other by Through Silicon vias (TSVs) such that logic blocks spread between layers. This architecture can reduce the wire length and also routing congestion in case of a good placement and routing algorithm [4,5].…”

Section: Introductionmentioning

confidence: 99%

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage

2015

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“…The general solution to the problem is to move the two-dimensional (2D) FPGA design to the three-dimensional (3D) architecture [4]. The layers of logic of a 3D FPGA are stacked on top of each other instead of being spread across a 2D plane.…”

Section: Introductionmentioning

confidence: 99%

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

Hsu

Huang

Lee

2010

Circuit Theory & Apps

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SUMMARYThree-dimensional (3D) field programmable gate array (FPGA) has evoked significant interest in wirelength reduction for routing requirement. However, the complex design of the 3D switch boxes will limit the performance improvement and suffer from the area efficiency problems. This paper proposed a systematic graph model (SGM) for 3D switch boxes design to simplify the design process and reduce the storage memory for path programming. An interlaced 3D switch boxes and two-dimensional (2D) switch boxes placement topology is also presented in this paper to design the 3D FPGA architecture for area efficiency purpose. The 3D place and route tool and TSMC 0.18-m CMOS process parameters are used to support building the experimental flow for verification. Performance evaluation shows that about 50% storage memory reduction can be obtained by using the proposed SGM-based switch design approach. Additionally, compared with conventional architectures of 2D FPGA, the proposed scheme based on interlaced switch boxes placement approach can approximately achieve 20% delay-power product improvement and 43% area-delay product reduction.

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Exploring Alternative 3D FPGA Architectures: Design Methodology and CAD Tool Support

Cited by 13 publications

References 8 publications

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

A novel online hardware task scheduling and placement algorithm for 3D partially reconfigurable FPGAs

Three-dimensional switchbox multiplexing in emerging 3D-FPGAs to reduce chip footprint and improve TSV usage

Interlaced switch boxes placement for three‐dimensional FPGA architecture design

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