Exploring a Machine Learning Approach to Performance Driven Analog IC Placement

Li, Yaguang; Lin, Yishuang; Madhusudan, Meghna; Sharma, Arvind Kumar; Xu, Wenbin; Sapatnekar, Sachin S.; Harjani, Ramesh; Hu, Jiang

doi:10.1109/isvlsi49217.2020.00015

Cited by 22 publications

(8 citation statements)

References 14 publications

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“…Bayesian Optimization [95] routing VAE [174] Post-layer Evaluation electromagnetic properties estimation GNN [165] performance prediction SVM, random forest, NN [84] CNN [94] GNN [83] deploying the model. Thus, ML-based methods have more potential in large scale applications at the cost of increased training costs.…”

Section: 34mentioning

confidence: 99%

“…So many researchers focus on layout performance prediction with ML algorithms. Li et al [84] compare the prediction accuracy of three classical ML algorithms: SVM, random forest and nerual network. They also combine the performance prediction algorithms with simulated annealing to fulfill an automated layout framework.…”

Section: Machine Learning For Electronic Design Automation: a Survey ...mentioning

confidence: 99%

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Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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With the down-scaling of CMOS technology, the design complexity of very large-scale integrated (VLSI) is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 90s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interests in incorporating ML to solve EDA tasks. In this paper, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

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Section: 34mentioning

confidence: 99%

Section: Machine Learning For Electronic Design Automation: a Survey ...mentioning

confidence: 99%

Machine Learning for Electronic Design Automation: A Survey

Huang

et al. 2021

Preprint

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“…For instance, an electrical constraint may be translated to a maximum limit on the resistance of a wire connecting two nodes, which in turn corresponds to a constraint on the maximum length, the number of parallel metal tracks, and the number of vias on the route connecting these nodes. This feature is currently being implemented in ALIGN [10], [11] and is a work in progress. The essential idea is to develop a fast ML inference engine that operates within the inner loop of an iterative placer, and for each placer configuration, determines whether or not its electrical constraints are satisfied.…”

Section: Constraint Generationmentioning

confidence: 99%

ALIGN: A System for Automating Analog Layout

Dhar¹,

Kunal²,

Li³

et al. 2020

Preprint

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ALIGN ("Analog Layout, Intelligently Generated from Netlists") is an open-source automatic layout generation flow for analog circuits. ALIGN translates an input SPICE netlist to an output GDSII layout, specific to a given technology, as specified by a set of design rules. The flow first automatically detects hierarchies in the circuit netlist and translates layout synthesis to a problem of hierarchical block assembly. At the lowest level, parameterized cells are generated using an abstraction of the design rules; these blocks are then assembled under geometric and electrical constraints to build the circuit layout. ALIGN has been applied to generate layouts for a diverse set of analog circuit families: low frequency analog blocks, wireline circuits, wireless circuits, and power delivery circuits.

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“…In [13], a generative neural networks (GNN) is trained to specify the area where the most suitable routing should exist. Li et al used supervised learning to conduct performancedriven analog IC placement [14]. They used several machine learning methods such as neural network and support vector machine (SVM) to predict the performance of placement solutions.…”

Section: Introductionmentioning

confidence: 99%

Analog Layout Placement for FinFET Technology Using Reinforcement Learning

Ahmadi

Zhang

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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Despite all efforts being made to ease analog layout generation, the designers' expertise is still highly demanded in the process of analog IC physical design. Recently, some endeavors started to leverage artificial intelligence (AI) to tackle the complexity of analog layout optimization and alleviate the high demand for the designers' experience in the design process. However, these methods, which mainly rely on using the previous designs, are not effective to the unseen data (or scenarios) that were not included in the AI training. In this paper, we have proposed a reinforcement-learning-based method that can fully automate analog layout placement optimization. It is not only applicable to any unseen analog placement scenarios, but also can meet the requirements of analog layout placement designs in the advanced FinFET technology. Our experimental results show that the proposed method can place analog modules subject to the defined objectives 77x faster than the conventional analytical methods (e.g., conjugate gradient) without compromising the optimization accuracy.

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Exploring a Machine Learning Approach to Performance Driven Analog IC Placement

Cited by 22 publications

References 14 publications

Machine Learning for Electronic Design Automation: A Survey

Machine Learning for Electronic Design Automation: A Survey

ALIGN: A System for Automating Analog Layout

Analog Layout Placement for FinFET Technology Using Reinforcement Learning

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