Exploration of Sub-VT and Near-VT 2T Gain-Cell Memories for Ultra-Low Power Applications under Technology Scaling

Abstract

Ultra-low power applications often require several kb of embedded memory and are typically operated at the lowest possible operating voltage (VDD) to minimize both dynamic and static power consumption. Embedded memories can easily dominate the overall silicon area of these systems, and their leakage currents often dominate the total power consumption. Gain-cell based embedded DRAM arrays provide a high-density, low-leakage alternative to SRAM for such systems; however, they are typically designed for operation at nominal or only slightly scaled supply voltages. This paper presents a gain-cell array which, for the first time, targets aggressively scaled supply voltages, down into the subthreshold (sub-VT) domain. Minimum VDD design of gain-cell arrays is evaluated in light of technology scaling, considering both a mature 0.18 μm CMOS node, as well as a scaled 40 nm node. We first analyze the trade-offs that characterize the bitcell design in both nodes, arriving at a best-practice design methodology for both mature and scaled technologies. Following this analysis, we propose full gain-cell arrays for each of the nodes, operated at a minimum VDD. We find that an 0.18 μm gain-cell array can be robustly operated at a sub-VT supply voltage of 400mV, providing read/write availability over 99% of the time, despite refresh cycles. This is demonstrated on a 2 kb array, operated at 1 MHz, exhibiting full functionality under parametric variations. As opposed to sub-VT operation at the mature node, we find that the scaled 40 nm node requires a near-threshold 600mV supply to achieve at least 97% read/write availability due to higher leakage currents that limit the bitcell’s retention time. Monte Carlo simulations show that a 600mV 2 kb 40 nm gain-cell array is fully functional at frequencies higher than 50 MHz

Statistical Analysis and Comparison of 2T and 3T1D e-DRAM Minimum Energy Operation

“…The spice net-lists of the 2T and 3T1D gain-cells are simulated in HSPICE [18] circuit simulator. The e-DRAMs were shown to perform reliably in nearthreshold region at 40nm node in [16]. So in this paper, e-DRAM gain-cells are studied at the next scaled technology node 32nm (using HP PTM models [19]) which is going to be the technology node for the future sub-threshold circuit implementations.…”

“…As an alternative to SRAM bit-cells, Meinerzhagen et.al. [16] investigated sub-threshold 2T e-DRAM gain-cells for ultra-low power medical applications. Their study showed reliable operation for 2kb e-DRAM array up to sub-threshold voltage of 0.4V at mature 0.18µm node and up to near-threshold voltage of 0.6V at scaled 40nm node.…”

Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM

“…This level can be read out by predischarging the read bitline (RBL) and subsequently raising the read wordline (RWL), conditionally charging RBL if the voltage level stored on SN is low. The circuit's leakage power, shown to be dominated by subthreshold conduction at submicron process technologies [4], is extremely low, since during standby and write, the drain-to-source voltage (V DS ) of MR is zero, and the subthreshold leakage through MW is limited to (dis)charging the storage capacity of SN. The obvious issue is that any leakage to or from SN results in a degradation of the stored data level, requiring periodic refresh cycles.…”

“…Furthermore, the subthreshold leakage to/from C SN is exponentially dependent on the overdrive of MW, which is constant for the worst-case of '0' storage (WBL=V DD ) but self limiting in the case of '1' degradation (WBL=0, V SG = V SN − V DD ). A full description of these processes is presented in [4].…”

“…In contrast to 1-Transistor 1-Capacitor (1T-1C) eDRAM solutions that require special process steps to implement large in-cell storage capacitors, GC-eDRAM is logic compatible and relies on parasitic (device) capacitances for charge storage. The authors of [3] and [4] have shown that the use of a highthreshold (HVT) or I/O transistor is the best choice for the implementation of a GC's write transistor. Retention times of several milliseconds have been shown in mature, 0.18µm CMOS technologies, appropriate for the fabrication of ULP applications, such as biomedical sensors [3], [7].…”