Exploration of Full HD Media Decoding on SDR Baseband Processor

Chen, Mei; Li, Min; Cao, Peng; Amin, Amir; Li, Chunshu; Pollin, Sofie; Yang, Jun

doi:10.1109/sips.2012.48

Cited by 1 publication

(1 citation statement)

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“…The parallel characteristics of the different algorithm tasks are analyzed and evaluated with respect to the processor properties. Previous work [6] has mapped two kernels of the decoder, and this work optimizes all the four data-intensive tasks, including the motion compensation (MC), the intra prediction, inverse integer transform and the deblocking filter. Results show that, with limited architectural extensions, a recent version of the ADRES based SDR baseband processor can process full HD H.264/AVC video (1920 1080) at 30 fps (frames per second).…”

Section: Introductionmentioning

confidence: 99%

Exploration of Full HD Media Decoding on a Software Defined Radio Baseband Processor

Chen

Cao

et al. 2013

IEEE Trans. Signal Process.

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Recently, various specialized Software Defined Radio (SDR) baseband processors have been proposed for meeting the high performance and programmability requirements for emerging wireless communication applications. In order to support high throughput wireless communication, the SDR baseband processors typically employ many parallel computation elements, which may also be used for performing other signal processing applications. This paper explores the feasibility of performing complex media processing on such SDR baseband processors. Specifically, the full HD 1080p state-of-the-art H.264/AVC media decoding has been implemented onto a recent version of the ADRES based SDR baseband processor. Since the processor was originally designed exclusively for wireless baseband applications, algorithm and architecture co-optimizations are required to make the goal feasible. Following algorithm analysis, the computationally dominant tasks of the H.264/AVC, including the motion compensation, the intra prediction, the inverse integer transform, and the deblocking filter, have been selected to be mapped onto the ADRES. The experimental results show that, with limited architectural extensions, the ADRES based baseband processor achieves competitive performance efficiency, even compared with several processors that are specifically optimized for the media decoding application.Index Terms-Baseband processor, H.264/AVC decoder, full HD, SIMD.

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Section: Introductionmentioning

confidence: 99%