Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking

Bischoff, G.; Brace, Karl S.; Cabodi, Gianpiero; Nocco, Sergio; Quer, Stefano

doi:10.1016/j.entcs.2004.06.061

Cited by 4 publications

(6 citation statements)

References 14 publications

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“…The approach is severely limited by the fact that it invokes BDD-based model checking only once, and therefore may run into severe memory blowup. In contrast, we interleave state traversal with path-based reasoning at finer granularity, rather than invoke the state-based approach only once as in [30].…”

Section: Related Workmentioning

confidence: 94%

“…The difference is that such initial state constraints are not precise (as is in our case), and therefore needs multiple refinement steps. In [30], a state-based approach using BDDs is applied to obtain a set of reachable set for some bound. This reachable set is then used as an initial state constraint for witness search in a stateless approach using SAT-based BMC.…”

Section: Related Workmentioning

confidence: 99%

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Efficient state space exploration: Interleaving stateless and state-based model checking

Ganai¹,

Wang²,

Li³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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State-based model checking methods comprise computing and storing reachable states, while stateless model checking methods directly reason about reachable paths using decision procedures, thereby avoiding computing and storing the reachable states. Typically, statebased methods involve memory-intensive operations, while stateless methods involve time-intensive operations. We propose a divide-andconquer strategy to combine the complementary strengths of these methods for efficient verification of embedded software. Specifically, our model checking engine uses both state decomposition and state prioritization to guide the combination of a Presburger arithmetic based symbolic traversal algorithm (state-based) and an SMT based bounded model checking algorithm (stateless). These two underlying algorithms are interleaved-based on memory/time bounds and dynamic task partitioning-in order to systematically explore the state space and to avoid storing the entire reachable state set. We have implemented our new method in a tightly integrated verification tool called HMC (Hybrid Model Checker). We demonstrate the efficacy of the proposed method on some industry examples.

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Section: Related Workmentioning

confidence: 94%

Section: Related Workmentioning

confidence: 99%

Efficient state space exploration: Interleaving stateless and state-based model checking

Ganai¹,

Wang²,

Li³

2010

2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

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“…In contrast we use a given set of unsatisfiability proofs (traces) to construct an abstract model, which is then used to extend the traces to desired future states. In an earlier work, Bischoff et al [5] proposed another 'dynamic abstraction' technique that builds an under-approximate set of reachable states using a breadth-first traversal of a corresponding BDD, which is then used to perform a SAT-based verification. In contrast, we use a known set of reachable states and their corresponding traces, which we then use to perform a SAT-based verification.…”

Section: Related Workmentioning

confidence: 99%

Trace based reachability verification for statecharts

Madhukar

Metta

Shrotri

et al. 2013

2013 1st FME Workshop on Formal Methods in Software Engineering (FormaliSE)

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Statecharts are widely used to model the behavior of reactive systems. While this visual formalism makes modeling easier, the state of the art in verification of statechart specifications is far from satisfactory due to the state explosion problem. We present History Abstraction, a trace-based verification technique to address this problem. Given a set of traces in a statechart model, the model is abstracted to contain at most three states per statechart: current, history and future. A path to a desired state in the abstract model is a sketch of a potential path to that state in the original model. We follow an incremental concretization procedure to extend the sketch to a complete path in the original model. This paper presents our technique. Our experiments suggest that the technique scales to large industry models.

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“…Bischoff et al [19] propose a methodology to use BDDs and SAT solvers for the verification of programs. The BDDs Benchmark are responsible for the target enlargement, collecting the under-approximate reachable state sets, followed by the SATbased verification with the newly computed sets.…”

Section: Related Workmentioning

confidence: 99%

Towards counterexample-guided k-induction for fast bug detection

Gadelha

Monteiro

Cordeiro

et al. 2018

Proceedings of the 2018 26th ACM Joint Meeting on European Software Engineering Conference and Symposium on the Foundations of

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Recently, the k-induction algorithm has proven to be a successful approach for both finding bugs and proving correctness. However, since the algorithm is an incremental approach, it might waste resources trying to prove incorrect programs. In this paper, we propose to extend the k-induction algorithm in order to shorten the number of steps required to find a property violation. We convert the algorithm into a meet-in-the-middle bidirectional search algorithm, using the counterexample produced from over-approximating the program. The preliminary results show that the number of steps required to find a property violation is reduced to ⌊ k 2 +1⌋ and the verification time for programs with large state space is reduced considerably.

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Exploiting Target Enlargement and Dynamic Abstraction within Mixed BDD and SAT Invariant Checking

Cited by 4 publications

References 14 publications

Efficient state space exploration: Interleaving stateless and state-based model checking

Efficient state space exploration: Interleaving stateless and state-based model checking

Trace based reachability verification for statecharts

Towards counterexample-guided k-induction for fast bug detection

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