Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

Suriano, Leonardo; Otero, Andrés; Rodríguez, Alonso Mateos; Sánchez‐Renedo, Manuel; Torre, Eduardo de la

doi:10.1109/access.2020.3005202

Cited by 7 publications

(7 citation statements)

References 47 publications

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“…From our study on the algorithm, it turned out that segmentation could be used to reduce the execution time, at the price of adopting more iterations of the DLS with respect to a classical sequential solution. Such a price could worth to be paid in strictly timing constrained scenarios, and a parallel hardware implementation like the one presented in [31] for the Nelder Mead IK solver could be adopted. The coprocessing infrastructure presented in Figure 17 is already compliant [5] with the parallel FPGA-based architecture presented in [4] and used in [31] for robotic purposes.…”

Section: Discussionmentioning

confidence: 99%

“…Such a price could worth to be paid in strictly timing constrained scenarios, and a parallel hardware implementation like the one presented in [31] for the Nelder Mead IK solver could be adopted. The coprocessing infrastructure presented in Figure 17 is already compliant [5] with the parallel FPGA-based architecture presented in [4] and used in [31] for robotic purposes. Therefore, in future, a parallel hardware implementation of the DLS could be certainly attempted.…”

Section: Discussionmentioning

confidence: 99%

“…matrix multiplications. Suriano et al [31] instead adopted the iterative Nelder-Mead optimization method to solve the IK problem, investing effort in parallelizing the application in different ways (intra-and inter-iteration). The resulting parallel solutions are then ported on an FPGA fabric tightly coupled with a multi-core system: the application is split between general purpose and dedicated computing units, which are provided in several instances enabling multi-parallelism on the hardware acceleration side.…”

Section: A Hardware Implementations Of Inverse Kinematic Solversmentioning

confidence: 99%

“…Table 2 summarizes the described IK solvers hardware implementations together with the approach proposed in this work. The analyzed state-of-the-art works adopt algorithms that are not suitable for the manipulator that is used in this work [2], [28], or algorithms that are meant for application fields far from the one considered in this paper [29], or even algorithms that might not converge [31]. As already said, we adopted the DLS that has a predictable convergence time for a given trajectory length, and it is capable of tolerating singularities in the workspace.…”

Section: A Hardware Implementations Of Inverse Kinematic Solversmentioning

confidence: 99%

“…In this case, programmers can play with three parameters: the damping factor, the number of iterations in the first DLS step and the number of iterations in the second DLS step. The parallel implementation has been considered to understand the potential benefits of implementing the DLS over a parallel computing infrastructure, as the one used in [31]. Clearly, due to physical hardware limitations, we cannot assume an infinite parallel factor.…”

Section: Workmentioning

confidence: 99%

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Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Fanni

Rubattu

et al. 2020

IEEE Access

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Modern embedded computing platforms used within Cyber-Physical Systems (CPS) are nowadays leveraging more and more often on heterogeneous computing substrates, such as newest Field Programmable Gate Array (FPGA) devices. Compared to general purpose platforms, which have a fixed datapath, FPGAs provide designers the possibility of customizing part of the computing infrastructure, to better shape the execution on the application needs/features, and offer high efficiency in terms of timing and power performance, while naturally featuring parallelism. In the context of FPGA-based CPSs, this paper has a two fold mission. On the one hand, it presents an analysis of the Damped Least Square (DLS) algorithm for a perspective hardware implementation. On the other hand, it describes the implementation of a robotic arm controller based on the DLS to numerically solve Inverse Kinematics problems over a heterogeneous FPGA. Assessments involve a Trossen Robotics WidowX robotic arm controlled by a Digilent ZedBoard provided with a Xilinx Zynq FPGA that computes the Inverse Kinematic.

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Section: Discussionmentioning

confidence: 99%

Section: Discussionmentioning

confidence: 99%

Section: A Hardware Implementations Of Inverse Kinematic Solversmentioning

confidence: 99%

Section: A Hardware Implementations Of Inverse Kinematic Solversmentioning

confidence: 99%

Section: Workmentioning

confidence: 99%

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Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Fanni

Rubattu

et al. 2020

IEEE Access

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Parallel Applications Mapping onto Heterogeneous MPSoCs Interconnected Using Network on Chip

Belkacemi

Daoui

Bouzefrane

2021

Lecture Notes in Computer Science

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To meet the growing requirements of today's applications, multiprocessor architectures (MPSoCs) interconnected with a network on chip (NoC) are considered as a major solution for future powerful embedded systems. Mapping phase is one of the most critical challenge in designing these systems. It consists of assigning application' tasks on the target platform which can have a considerable influence on the performance of the final system. Due to the large solutions' research space generated by both the application complexity and the platforms, this mapping phase can no longer be done manually and hence it requires powerful exploration tools called DSE (Design Space Exploration Environment). This paper proposes a new tool for static mapping applications on NoC based on heterogeneous MPSoCs. This tool integrates several multiobjective optimization algorithms that can be specified in order to explore different solutions' spaces, mainly: exact method, metaheuristics (population-based metaheuristics and single solution-based ones) as well as hybrid ones; it offers different cost functions (defined using analytical or simulation models). The user can specify them or define others easily and it provides an easy way to evaluate the performance of the Pareto front returned by different algorithms using multiple quality indicators. We also present a series of experiments by considering several scenarios and give guidelines to designers on choosing the appropriate algorithm based on the characteristics of the mapping problem considered.

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An Automated Design Flow for Adaptive Neural Network Hardware Accelerators

Ratto

Máinez

et al. 2023

J Sign Process Syst

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Image and video processing are one of the main driving application fields for the latest technology advancement of computing platforms, especially considering the adoption of neural networks for classification purposes. With the advent of Cyber Physical Systems, the design of devices for efficiently executing such applications became more challenging, due to the increase of the requirements to be considered, of the functionalities to be supported, as well as to the demand for adaptivity and connectivity. Heterogeneous computing and design automation are then turning into essential. The former guarantees a variegated set of features under strict constraints (e.g., by adopting hardware acceleration), and the latter limits development time and cost (e.g., by exploiting model-based design). In this context, the literature is still lacking adequate tooling for the design and management of neural network hardware accelerators, which can be adaptable and customizable at runtime according to the user needs. In this work, a novel almost automated toolchain based on the Open Neural Network eXchange format is presented, allowing the user to shape adaptivity right on the network model and to deploy it on a runtime reconfigurable accelerator. As a proof of concept, a Convolutional Neural Network for human/animal classification is adopted to derive a Field Programmable Gate Array accelerator capable of trading execution time for power by changing the resources involved in the computation. The resulting accelerator, when necessary, can consume 30% less power on each layer, taking about overall 8% more time to classify an image.

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Exploiting Multi-Level Parallelism for Run-Time Adaptive Inverse Kinematics on Heterogeneous MPSoCs

Cited by 7 publications

References 47 publications

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA

Parallel Applications Mapping onto Heterogeneous MPSoCs Interconnected Using Network on Chip

An Automated Design Flow for Adaptive Neural Network Hardware Accelerators

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