Exploiting Data-Parallelism on Multicore and SMT Systems for Implementing the Fractal Image Compressing Problem

Abstract

This paper presents a parallel modeling of a lossy image compression method based on the fractal theory and its evaluation over two versions of dual-core processors: with and without simultaneous multithreading (SMT) support. The idea is to observe the speedup on both configurations when changing application parameters and the number of threads at operating system level. Our target application is particularly relevant in the Big Data era. Huge amounts of data often need to be sent over low/medium bandwidth networks, and/or to be saved on devices with limited store capacity, motivating efficient image compression. Especially, the fractal compression presents a CPU-bound coding method known for offering higher indexes of file reduction through highly time-consuming calculus. The structure of the problem allowed us to explore data-parallelism by implementing an embarrassingly parallel version of the algorithm. Despite its simplicity, our modeling is useful for fully exploiting and evaluating the considered architectures. When comparing performance in both processors, the results demonstrated that the SMT-based one presented gains up to 29%. Moreover, they emphasized that a large number of threads does not always represent a reduction in application time. In average, the results showed a curve in which a strong time reduction is achieved when working with 4 and 8 threads when evaluating pure and SMT dual-core processors, respectively. The trend concerns a slow growing of the execution time when enlarging the number of threads due to both task granularity and threads management.

Deep Pipeline Architecture for Fast Fractal Color Image Compression Utilizing Inter-Color Correlation

“…From the table, it can be seen that the encoding time of the proposed architecture is the lowest compared to others, which corresponds to 2x, 133x, 11250x, 2125x and 116x less than [1], [2], [3], [4] and [6], respectively. If the image size is taken into account and knowing that the proposed design can encode 512×512×3 and 256×256×3 images in 3 ms and 0.75 ms, respectively, the proposed design exhibits 8x, 2133x, 11250x, 8500x and 1866x faster than [1], [2], [3], [4] and [6], respectively. From these figures, it is clearly that the proposed architecture is significantly superior to others.…”